Abstract: A method, system, apparatus, and computer program product is presented for processing instructions. A processor is able to receive multiple types of interruptions while executing instructions, such as aborts, faults, interrupts, and traps. A set of processor fields are used to indicate whether or not one or more trap modes are active, such as a single-step trap mode or a taken-branch trap mode. The activity of a trap mode is conditioned, i.e., restricted, modified, or qualified, with a trap mode conditioning field that indicates whether or not the trap mode should remain active during interruption processing. The use of a trap mode conditioning field allows an interruption handler to run at full speed without being interrupted by the trap mode, yet the trap mode is preserved so that other processing, such as instruction tracing, may continue after interruption processing.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor is in instrumentation mode in response to the processor executing a plurality of instructions. When the determination is made that the processor is in instrumentation mode, instrumentation instructions associated with the plurality of instructions are executed. The instrumentation instructions are unexecuted in response to an absence of the processor being in instrumentation mode.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A first processor identifies a target processor in response to the first processor executing a plurality of instructions in an instrumentation mode. The processor designates the target processor to execute instrumentation instructions associated with the plurality of instructions in response to identifying the target processor.

Abstract: A computer implemented method, apparatus and computer usable program code for marking instructions for instrumentation. A plurality of instructions is presented in a graphical user interface. A user input selecting a set of instructions in the plurality of instructions for instrumentation is received through the graphical user interface. A set of instructions is marked as a set of instrumentation instructions in response to receiving the user input. The set of instructions are executed by a processor if the processor is in an instrumentation mode, and the instrumentation instructions are unexecuted if an absence of the processor being in the instrumentation mode is present.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor executing a plurality of instructions is in an instrumentation mode. The processor has a normal set of resources and an alternate set of resources in which the alternate set of resources is associated with the instrumentation mode. When a determination is made that the processor is in the instrumentation mode, the processor executes instrumentation instructions in the plurality of instructions using the alternate set of resources and executes all other instructions in the plurality of instructions using the normal set of resources.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a set of instructions are a set of instrumentation instructions in response to identifying the set of instructions in instructions for execution. A further determination is made as to whether a processor executing the instructions is in an instrumentation mode if the set of instructions are instrumentation instructions. The processor executes the set of instrumentation instructions only if the processor is in the instrumentation mode.

Abstract: A computer implemented method, apparatus and computer program product for processing instructions. A determination is made as to whether an instruction is a start instrumentation instruction in response to identifying the instruction for execution while executing the instructions using a normal set of processor resources in a processor. Subsequent instructions are executed using an alternate set of processor resources until an end instrumentation instruction is encountered.

Abstract: A computer implemented method, apparatus, and computer usable medium for gathering performance related data in a multiprocessing environment. Instrumentation code is executed on a processor that minimizes the distortion to the processor resources used to execute the program to be profiled. Data is written by the instrumentation code to a shared memory in response to an event occurring during execution of the program. The data is generated during execution of the program on the processor and the instrumentation code uses shared memory to convey the data to a profiling application running on a set of profiling processors. The data is collected by the set of profiling processors in the shared memory written by the instrumentation code.

Abstract: A computer implemented method, apparatus, and computer usable program code for collecting information about threads. A thread entering a wait state is detected. Information is selectively obtained about a set of threads in the wait state using a policy to produce an action in response to the thread entering the wait state. A history containing the collected data may be saved and used to determine changes to patterns.

Abstract: A computer implemented method, apparatus, and computer usable program code to collect information for a system or processor having a transition between an idle state and a non-idle state to form collected system or processor information. The collected system or processor information is provided for analysis by an application.

Abstract: A computer implemented method, apparatus, and computer usable program code for adjusting rates at which events are generated or processed. In response to a frequency change in a processor, a frequency for the processor is identified. A rate at which samples of events generated by the processor are selected to meet a desired rate of sampling is adjusted in response to identifying the frequency change for the processor to form an adjusted rate.

Abstract: A computer implemented method, apparatus, and computer usable code for identifying processor utilization. A current event is detected. A number of elapsed cycles for a processor since a previous event are identified in response to detecting the current event. An elapsed time using the number of elapsed cycles and a current frequency of the processor is calculated, wherein the elapsed time is used to identify the processor utilization.

Abstract: A method, apparatus, and computer usable program code for managing trace records. A set of traces is generated for a set of processors. A trace is generated in the set of traces for each processor within the set of processors. A record of the frequency change is stored in the set of traces in response to a frequency change in a processor within the set of processors. Trace records are combined in the set of traces using the record of the frequency change to determine a correct order for the records.

Abstract: A method, apparatus, and computer instructions for determining computer flows autonomically using hardware assisted thread stack and cataloged symbolic data. When a new thread is spawned during execution of a computer program, new thread work area is allocated by the operating system in memory for storage of call stack information for the new thread. Hardware registers are set with values corresponding to the new thread work area. Upon context switch, values of the registers are saved in a context save area for future restoration. When call stack data is post-processed, the operating system or a device driver copies call stack data from the thread work areas to a consolidated buffer and each thread is mapped to a process. Symbolic data may be obtained based on the process identifier and address of the method/routine that was called/returned in the thread. Corresponding program flow is determined using retrieved symbolic data and call stack data.

Abstract: A method, apparatus, and computer instructions for local program reorganization using branch count per instruction hardware. In a preferred embodiment, a hardware counter is used in the present invention to count the number of times a branch is taken when branch instructions are executed. Branch count statistics generated from the hardware counters are available to a program in order to analyze whether code reorganization is necessary. If reorganization is necessary, the program autonomically reorganizes instructions locally at run time to allow more instructions to be executed prior to taking a branch, so that the number of branches taken is minimized without modifying underlying program code.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. there is a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators may be utilized to obtain information regarding the nature of the cache hits and reloads of cache lines within the instruction or data cache. These embodiments may be used to determine whether processors of a multiprocessor system, such as a symmetric multiprocessor (SMP) system, are truly sharing a cache line or if there is false sharing of a cache line. This determination may then be used as a means for determining how to better store the instructions/data of the cache line to prevent false sharing of the cache line.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality may be provided in the performance monitoring application for initiating the measurement of secondary metrics with regard to identified instructions, data addresses, ranges of identified instructions, or ranges of identified data addresses, based on counter values for primary metrics. Thus, for example, when a primary metric counter, or a combination of primary metric counters, meets or exceeds a predetermined threshold value, an interrupt may be generated. In response to receiving the interrupt, counters associated with the measuring of secondary metrics of a range of instructions/data addresses may be initiated.

Abstract: A method, apparatus and computer instructions for hardware assist for autonomically patching code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A method, apparatus, and computer instructions for counting interrupts by type. An interrupt count is incremented when a particular type of interrupt occurs. The count may be stored in the IDT or an interrupt count table outside the IDT. The interrupt unit increments the count each time a particular type of interrupt occurs. In the event of a potential count overflow, the mechanism of the present invention provides logic necessary to notify software in order to handle the overflow.