Abstract: A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.

Abstract: A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.

Abstract: A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.

Abstract: A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor.

Abstract: A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as well as the shared resources associated with other clusters.

Abstract: Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.