Abstract: A multischeme memory management system for large memory computer systems which combines traditional hardware based memory management with a versatile software based memory management scheme. The memory management system includes a conventional memory handler implemented in hardware for managing memory addresses below a fixed limit, for example four gigabytes; and a plurality of memory handlers implemented in software for managing memory addresses greater than four gigabytes. A programmable memory range detectors is associated with each software implemented memory handler. Memory handlers are selected by addressing the different memory address ranges programmed into the memory range detectors.

Abstract: An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.

Abstract: Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Abstract: Process migration is controlled in multiple processor system by a circuit providing a rapid lookup to see if an available process has any affinity for the top N entries on the system run queue. If the currently available processor has an affinity for, i.e. has one or more lines of operands and/or instructions stored in its local cache related to the process, then the processor selects the process it has affinity for from the top N processes on the run queue. In this manner, unnecessary replacements of cache lines with data from main memory is reduced.