Abstract: A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports.

Abstract: A system for upgrading a personal computer includes a motherboard having upgrade sockets for upgrading the CPU and the clock oscillator without the need to remove any components. The system includes sensing circuitry for detecting the type of component plugged into the upgrade socket and circuitry for disabling the upgraded component. In addition, the system includes software for reconfiguring various signals depending on the particular upgrade plugged into the upgrade socket. By providing a system that can be upgraded by merely inserting a newer components, upgrades can be performed rather quickly. In addition, the upgrade system allows the end user a plurality of upgrade options while at the same time allows the end user to take advantage of declining CPU prices.

Abstract: A control circuit which allows computer systems to modify signal timing relationships in the hardware via programmable ports in the system, thereby allowing timing adjustments to be made without effecting motherboard hardware. The control circuit includes a plurality of delay devices configured to provide a plurality of delays under program control. The control circuit is adapted to extend the duration of a write signal to enable data to be latched, normally on the trailing edge of the write signal to avoid latching invalid data.

Abstract: A system includes a system bus having data lines, an acknowledge line, an enable line, and a control line, a data storage device, a controller circuit, and an arrangement coupling the system bus, controller circuit and data storage device. The system bus can carry out a data transfer cycle in which the acknowledge, enable and control lines are actuated and the controller obtains and checks data from the data storage device and supplies it to data lines of the bus, and a verify cycle in which the acknowledge and enable lines are actuated and the control line is deactuated and the controller obtains and checks data from the storage device but does not supply it to the bus. The controller circuit is capable of operating in different modes, in one of which it forcibly sets a false error indication in response to the verify cycle.

Abstract: A vertically extending framework having a hydraulic ram subassembly mounted in the framework for pivotation about a horizontal axis, and spaced from the lower end of the framework to accommodate a refuse receptacle within the framework under the ram. A disinfectant injection pump is mounted in the hydraulic ram for automatically discharging a disinfectant into refuse compressed by the ram. The ram is double acting, and valve means is provided for automatically retracting the ram when a predetermined force opposes the outward extension of the piston of the ram.