Patents by Inventor Jimmy Earl Chambers

Jimmy Earl Chambers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8810592
    Abstract: One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 19, 2014
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, James C. Bowman, Jimmy Earl Chambers, Philip Browning Johnson, Philip Payman Shirvani
  • Publication number: 20110102448
    Abstract: One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs.
    Type: Application
    Filed: September 30, 2010
    Publication date: May 5, 2011
    Inventors: Ziyad S. HAKURA, James C. Bowman, Jimmy Earl Chambers, Philip Browning Johnson, Philip Payman Shirvani