Abstract: A latch-up-free ESD protection circuit using SCR is disclosed, in which an SCR is connected between the input pad and the negative power supply; a turn-on switch and a turn-off switch are connected between the positive power supply VDD (or the input pad) and the SCR; and a transistor gating circuit is connected to the turn-on switch and the turn-off switch to direct the operation of the SCR. When overvoltage stress develops over the input pad in the fast-transient mode, the turn-on switch enables the NPN transistor to switch on the SCR to form a discharging path for electrostatic discharge; and when overvoltage stress is released, the turn-off switch enables the PNP transistor to switch off the SCR, thus making it immune to any latch-up after the overvoltage stress is released, and having the advantages of fast triggering, low trigger voltage, no latch-up, and full ESD protection in the active and passive modes.

Abstract: A latch-up-free ESD protection circuit using SCR is disclosed, in which an SCR is connected between the input pad and the negative power supply; a turn-on switch and a turn-off switch are connected between the positive power supply VDD (or the input pad) and the SCR; and a transistor gating circuit is connected to the turn-on switch and the turn-off switch to direct the operation of the SCR. When overvoltage stress develops over the input pad in the fast-transient mode, the turn-on switch enables the NPN transistor to switch on the SCR to form a discharging path for electrostatic discharge; and when overvoltage stress is released, the turn-off switch enables the PNP transistor to switch off the SCR, thus making it immune to any latch-up after the overvoltage stress is released, and having the advantages of fast triggering, low trigger voltage, no latch-up, and full ESD protection in the active and passive modes.

Abstract: An ESD protection circuit is disclosed, including a silicon controlled switch (SCS), a switch control circuit, a metal oxide semiconductor field effect transistor (MOSFET), and a transistor control circuit, wherein when terminal over-voltage stress occurs over the positive power supply terminal in the active mode, the transistor control circuit is able to turn on the MOSFET, and at the same time the switch control circuit is able to trigger the SCS into conduction to form a discharging path, such that the terminal voltage over the positive power supply terminal will be rapidly decreased to the level of the holding voltage of the SCS to provide ESD protection for the IC. When terminal over-voltage stress in the active mode is removed, the MOSFET is disabled, but the SCS remains closed for discharge current, so the latch-up phenomenon is avoided.