Abstract: Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.

Abstract: A printed circuit board, according one embodiment, includes a reference layer; a dielectric layer disposed on the reference layer; and a conductor layer adhered to the dielectric layer with an adhesive layer disposed between the dielectric layer and the conductor layer. The conductor layer has a smooth surface facing the dielectric layer having a roughness (Rz) of less than two microns.

Abstract: A printed circuit board, according one embodiment, includes a reference layer; a dielectric layer disposed on the reference layer; and a conductor layer adhered to the dielectric layer with an adhesive layer disposed between the dielectric layer and the conductor layer. The conductor layer has a smooth surface facing the dielectric layer having a roughness (Rz) of less than two microns.

Abstract: Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.

Abstract: Techniques and mechanisms to mitigate noise in a signal line extending across rails arranged in a split plane configuration. In an embodiment, respective sides of a first rail and a second rail define opposite sides of a boundary region between the rails. The first rail forms a groove and the second rail forms a branch portion that extends at least in part into the groove. In another embodiment, one or more signal lines each extend across the boundary region and proximate to the branch portion, the one or more signals each to communicate a respective signal while the first rail is at a first voltage and while the second rail is at a second voltage. The branch portion and groove contribute to a reduced impedance discontinuity across the boundary region, which mitigates the creation of signal noise in the one or more signal lines.

Abstract: A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.

Abstract: A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.

Abstract: A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

Abstract: A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole and extended through the through hole. The reference line is disposed on a portion of the inner surface of the through hole and extended through the through hole, wherein the reference line is disposed between the lines for signal. Because the signal lines are separated by the reference line, the electromagnetic coupling generated by signals can be reduced to lower the cross-talk interference between signals passing through the through hole, so as to promote the signal-transmission quality.

Abstract: A signal transmission structure is provided. The structure mainly comprises at least a conductive via, at least a via land and a conductive wall. One end of the conductive via is connected to the via land. The conductive wall covers only a portion of the inner wall of a through hole in the core layer of a circuit substrate. The conductive wall has a semi-circular or a C-shaped structure. Therefore, when a signal passes the conductive via and the via land of the circuit substrate through the conductive wall in the interior of the via, because of a more continuous impedance between the via land and the conductive wall, signal reflection due to impedance mismatch along the signal transmission pathway can be reduced to enhance signal transmission quality.

Abstract: A multi-layered substrate has a voltage reference signal circuit layout therein. A major change in the design of the multi-layered substrate is the moving of a reference signal trace from a signal layer to a non-signaling layer. Once the reference signal trace is moved, the signal traces within the signal layer can have a larger layout area. Similarly, the reference signal trace within the non-signaling layer can have greater layout flexibility in addition to electromagnetic shielding from other signal traces. Moreover, the reference signal trace having a greater width may be used to reduce parasitic resistance within the reference signal circuit.

Abstract: The methodology includes a single excitation analysis, a multi-excitation analysis, and a simultaneous switch noise, SSN, analysis. A chip connects to the PDS at a plurality of power ports formed by pads for obtaining biasing voltage and current from those power ports. The single excitation analysis includes respectively making each of power ports start conducting current, and measuring a voltage provided by the power port. An equivalent impedance of each power port is obtained. The multi-excitation analysis includes making a given power port conduct a given current, and measuring voltages at other power ports for evaluating mutual couplings across different power ports. The SSN analysis includes respectively making different numbers of power ports conduct currents and accordingly evaluating different equivalent impedances corresponding to different SSN situations.

Abstract: A mechanism is provided for detecting when a wireless device is entering a quiet zone. An out-of-range condition is created in an entryway to a quiet zone. When a wireless device is in a transition zone, the device transmits a re-scan message with a unit identification in an attempt to reestablish communication with the communication tower. A re-scan receiver is provided in the entryway to receive re-scan messages and notify a mobile telephone switching office that the device is entering a quiet zone. The switching office then sends a ring type modifier property to the device when the device leaves the transition zone and reestablishes communications with the communication tower.

Abstract: A signal transmission structure including a signal line, a first reference plane with a first opening, and a second reference plane with a second opening is provided. The first reference plane is disposed beside the signal line, and a portion of the signal line passes through a position of the first opening. In addition, the second reference plane is disposed beside the first reference plane, and the second opening is in a position corresponding to the position of the first opening, while the outline of the second opening projected onto the first reference plane does not overlap with the position of the first opening. Therefore, at high frequency-transmission, the above structure can reduce the insertion loss resulted from impedance mismatch as the signal passes through the opening, and reduce the resonance induced by the coupling between two reference planes to enhance the quality of signal transmission.

Abstract: A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

Abstract: The methodology includes a single excitation analysis, a multi-excitation analysis, and a simultaneous switch noise, SSN, analysis. A chip connects to the PDS at a plurality of power ports formed by pads for obtaining biasing voltage and current from those power ports. The single excitation analysis includes respectively making each of power ports start conducting current, and measuring a voltage provided by the power port. An equivalent impedance of each power port is obtained. The multi-excitation analysis includes making a given power port conduct a given current, and measuring voltages at other power ports for evaluating mutual couplings across different power ports. The SSN analysis includes respectively making different numbers of power ports conduct currents and accordingly evaluating different equivalent impedances corresponding to different SSN situations.

Abstract: A signal transmission structure is provided. The signal transmission structure has salients. The salients are corresponding to the position of the non-reference region and protrude from a lateral side of the signal traces. When the signals are transmitted on the signal traces, the parasitic capacitance between the salients and the reference plane can improve the characteristic impedance mismatch. Hence, when the signals are transmitted in a high frequency/high speed environment, the salients of the signal transmission structure reduce the effect of the near-end and far-end crosstalk generated by the other signal trace when a signal trace passes through a non-reference region, in order to keep the good quality of the signals.

Abstract: The chip package comprising a package substrate, a circuit layer, a chip and at least one conductive wire is provided. The circuit layer is disposed on a first surface of the substrate, and extends from the first surface to a second surface of the substrate via the inner surface of a slot of the substrate. The chip is disposed on the second surface of the substrate to cover the slot and a portion of the circuit layer. The chip has at least one signal pad and at least one non-signal pad. The non-signal pad is electrically connected to the circuit layer on the second surface. The slot in the substrate exposes the signal pad. One end of the conductive wire passing through the slot is connected to the signal pad while the other end thereof is connected to the circuit layer on the first surface of the substrate.