Patents by Inventor Jimmy Jason Tomblin

Jimmy Jason Tomblin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hierarchical fill in a design layout
    Patent number: 9940428
    Abstract: This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: April 10, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Fedor Pikus, Jimmy Jason Tomblin, William S. Graupp
  • HIERARCHICAL FILL IN A DESIGN LAYOUT
    Publication number: 20160098512
    Abstract: This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 7, 2016
    Inventors: Fedor Pikus, Jimmy Jason Tomblin, William S. Graupp
  • Voltage-related analysis of layout design data
    Patent number: 9262574
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for voltage-related analysis of layout design data. According to embodiments of the disclosed technology, voltage association data objects are generated for drawn layers in a net of a layout design and voltage values or ranges of voltage values associated with the net are collected. The voltage values or ranges of voltage values are then associated with the voltage association data objects. A voltage-related analysis may be performed by searching the voltage association data objects according to a predetermined criterion.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 16, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Jimmy Jason Tomblin, Laurence Grodd
  • VOLTAGE-RELATED ANALYSIS OF LAYOUT DESIGN DATA
    Publication number: 20140189613
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for voltage-related analysis of layout design data. According to embodiments of the disclosed technology, voltage association data objects are generated for drawn layers in a net of a layout design and voltage values or ranges of voltage values associated with the net are collected. The voltage values or ranges of voltage values are then associated with the voltage association data objects. A voltage-related analysis may be performed by searching the voltage association data objects according to a predetermined criterion.
    Type: Application
    Filed: December 18, 2013
    Publication date: July 3, 2014
    Applicant: Mentor Graphics Corporation
    Inventors: Jimmy Jason Tomblin, Laurence Grodd