Patents by Inventor Jimmy Jianan Kan

Jimmy Jianan Kan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10833254
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 10, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Chando Park, Jimmy Jianan Kan, Peiyuan Wang, Seung Hyuk Kang
  • Patent number: 10547460
    Abstract: Exemplary features pertain to secure communications using Physical Unclonable Function (PUF) devices. Segments of a message to be encrypted are sequentially applied to a PUF device as a series of challenges to obtain a series of responses for generating a sequence of encryption keys, whereby a previous segment of the message is used to obtain a key for encrypting a subsequent segment of the message. The encrypted message is sent to a separate (receiving) device that employs a logical copy of the PUF device for decrypting the message. The logical copy of the PUF may be a lookup table or the like that maps all permissible challenges to corresponding responses for the PUF and may be generated in advance and stored in memory of the receiving device. The data to be encrypted may be further encoded to more fully exercise the PUF to enhance security. Decryption operations are also described.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 28, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Peiyuan Wang, Chando Park, Jimmy Jianan Kan, Seung Hyuk Kang
  • Patent number: 10431734
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Jimmy Jianan Kan, Peiyuan Wang, Seung Hyuk Kang
  • Publication number: 20190288187
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Inventors: Chando PARK, Jimmy Jianan KAN, Peiyuan WANG, Seung Hyuk KANG
  • Patent number: 10381060
    Abstract: A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells may include a perpendicular magnetic tunnel junction (pMTJ) including a reference layer, a barrier layer supporting the reference layer, and a free layer supporting the barrier layer. A spin-hall conductive material layer may support the free layer. A driver may be operable to set a state of at least one of the bit cells using an increased spin-transfer torque (STT) current and a spin-hall effect from the spin-hall conductive material layer. The increased STT current may be driven through the spin-hall conductive material layer and the pMTJ so that a spin current is generated from the reference layer and the spin-hall conductive material layer.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 13, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jimmy Jianan Kan, Chando Park, Peiyuan Wang, Sungryul Kim, Seung Hyuk Kang
  • Patent number: 10224368
    Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jimmy Jianan Kan, Seung Hyuk Kang, Bin Yang, Gengming Tao
  • Publication number: 20190006415
    Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Xia Li, Jimmy Jianan Kan, Seung Hyuk Kang, Bin Yang, Gengming Tao
  • Patent number: 10134808
    Abstract: Magnetic tunnel junction (MTJ) devices with a heterogeneous free layer structure particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer section provided below a first tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer section includes one pinned layer magnetized in one magnetic orientation. In another aspect, a second pinned layer section and a second TMR barrier layer are provided above a free layer section and above the first TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel (AP) to that of the first pinned layer section. In yet another aspect, the free layer comprises first and second heterogeneous layers separated by an anti-ferromagnetic coupling spacer, the first and second heterogeneous layers differing in their magnetic anisotropy.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jimmy Jianan Kan, Chando Park, Matthias Georg Gottwald, Seung Hyuk Kang
  • Patent number: 10096649
    Abstract: Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of the MTJ device. In this manner, etching of the bottom electrode may be reduced or avoided to reduce or avoid metal redeposition as a result of over-etching the MTJ device to avoid horizontal shorts between an adjacent device(s). In another example, a seed layer is embedded in a bottom electrode of the MTJ device. In this manner, the MTJ stack is reduced in height to reduce or avoid metal redeposition as a result of over-etching the MTJ device. In another example, an MTJ device includes an embedded seed layer in a bottom electrode which also has a width less than a width of the MTJ stack.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Jimmy Jianan Kan, Seung Hyuk Kang
  • Publication number: 20180266991
    Abstract: Magneto-impedance (MI) sensors employing current confinement and exchange bias layer(s) for increased MI sensitivity are disclosed. MI sensors may be used as biosensors to detect biological materials. The sensing by the MI devices is based on a giant magneto-impedance (GMI) effect, which is very sensitive to a magnetic field. The GMI effect is a change in impedance of a magnetic material resulting from a change in skin depth of the magnetic material as a function of an external direct current (DC) magnetic field applied to the magnetic material and an alternating current (AC) current flowing through the magnetic material (or adjacent conductive materials). Thus, this change in impedance resulting from a magnetic stray field generated by magnetic nanoparticles can be detected in lower concentrations and measured to determine the amount of magnetic nanoparticles present, and thus the target analyte of interest.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 20, 2018
    Inventors: Jimmy Jianan Kan, Peiyuan Wang, Chando Park, Seung Hyuk Kang
  • Publication number: 20180212142
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 26, 2018
    Inventors: Chando PARK, Jimmy Jianan KAN, Peiyuan WANG, Seung Hyuk KANG
  • Publication number: 20180145838
    Abstract: Exemplary features pertain to secure communications using Physical Unclonable Function (PUF) devices. Segments of a message to be encrypted are sequentially applied to a PUF device as a series of challenges to obtain a series of responses for generating a sequence of encryption keys, whereby a previous segment of the message is used to obtain a key for encrypting a subsequent segment of the message. The encrypted message is sent to a separate (receiving) device that employs a logical copy of the PUF device for decrypting the message. The logical copy of the PUF may be a lookup table or the like that maps all permissible challenges to corresponding responses for the PUF and may be generated in advance and stored in memory of the receiving device. The data to be encrypted may be further encoded to more fully exercise the PUF to enhance security. Decryption operations are also described.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Peiyuan Wang, Chando Park, Jimmy Jianan Kan, Seung Hyuk Kang
  • Publication number: 20180061467
    Abstract: A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells may include a perpendicular magnetic tunnel junction (pMTJ) including a reference layer, a barrier layer supporting the reference layer, and a free layer supporting the barrier layer. A spin-hall conductive material layer may support the free layer. A driver may be operable to set a state of at least one of the bit cells using an increased spin-transfer torque (STT) current and a spin-hall effect from the spin-hall conductive material layer. The increased STT current may be driven through the spin-hall conductive material layer and the pMTJ so that a spin current is generated from the reference layer and the spin-hall conductive material layer.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Jimmy Jianan KAN, Chando PARK, Peiyuan WANG, Sungryul KIM, Seung Hyuk KANG
  • Publication number: 20180040668
    Abstract: Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of the MTJ device. In this manner, etching of the bottom electrode may be reduced or avoided to reduce or avoid metal redeposition as a result of over-etching the MTJ device to avoid horizontal shorts between an adjacent device(s). In another example, a seed layer is embedded in a bottom electrode of the MTJ device. In this manner, the MTJ stack is reduced in height to reduce or avoid metal redeposition as a result of over-etching the MTJ device. In another example, an MTJ device includes an embedded seed layer in a bottom electrode which also has a width less than a width of the MTJ stack.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 8, 2018
    Inventors: Chando Park, Jimmy Jianan Kan, Seung Hyuk Kang
  • Patent number: 9870811
    Abstract: In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Peiyuan Wang, Jung Pill Kim, Jimmy Jianan Kan, Chando Park, Seung Kang
  • Publication number: 20170365316
    Abstract: In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.
    Type: Application
    Filed: June 17, 2016
    Publication date: December 21, 2017
    Inventors: Peiyuan Wang, Jung Pill Kim, Jimmy Jianan Kan, Chando Park, Seung Kang
  • Patent number: 9824735
    Abstract: An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jimmy Jianan Kan, Chando Park, Peiyuan Wang, Seung Hyuk Kang
  • Patent number: 9704919
    Abstract: High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed. In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers. In one aspect, the coupling column comprises a high aspect ratio via. In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column. In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Lu, Wei-Chuan Chen, Jimmy Jianan Kan, Seung Hyuk Kang
  • Publication number: 20170125481
    Abstract: Magnetic tunnel junction (MTJ) devices with a heterogeneous free layer structure particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer section provided below a first tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer section includes one pinned layer magnetized in one magnetic orientation. In another aspect, a second pinned layer section and a second TMR barrier layer are provided above a free layer section and above the first TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel (AP) to that of the first pinned layer section. In yet another aspect, the free layer comprises first and second heterogeneous layers separated by an anti-ferromagnetic coupling spacer, the first and second heterogeneous layers differing in their magnetic anisotropy.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 4, 2017
    Inventors: Jimmy Jianan Kan, Chando Park, Matthias Georg Gottwald, Seung Hyuk Kang
  • Publication number: 20170077387
    Abstract: Magnetic Tunnel Junction (MTJ) devices particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer provided below a tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer provided below the TMR bather layer includes one pinned layer magnetized in only one magnetic orientation. In another aspect, a second pinned layer and a spacer layer are provided above a free layer and the TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel to that of the first pinned layer. In yet another aspect, a giant magneto-resistance (GMR) spacer layer is provided as the spacer layer between the second pinned layer and the free layer in the MTJ.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 16, 2017
    Inventors: Jimmy Jianan Kan, Matthias Georg Gottwald, Xiaochun Zhu, Chando Park, Seung Hyuk Kang