Abstract: A thin film resistor structure includes a plurality of thin film resistor sections. Conductive vias (5) are disposed on a first end of each of the thin film resistor sections, respectively. The first conductor (2) is connected to the vias of the first end, and a second conductor (3) is connected to vias on a second end of each of the thin film resistor sections. A distribution of a parameter of a batch of circuits including the thin film resistor structure indicates a systematic error in resistance values. Based on analysis of the distribution and the circuit, or more of the vias are individually moved at the layout grid level by a layout grid address unit to reduce the systematic error by making corresponding adjustments on a via reticle of a mask set used for making the circuits. Expensive laser trimming of thin film resistors of the circuit is thereby avoided.

Abstract: A digital-to-analog converter includes a resistive divider network including a plurality of series resistors of resistance R and a plurality of shunt resistors of resistance 2R' and a circuit for switching a shunt resistor of the resistive divider network in the digital-to-analog converter to either of first and second reference voltages. The switching circuit includes a first switch MOSFET coupling the low reference voltage to the shunt resistor, and a second switch MOSFET coupling the shunt resistor to the high reference voltage. First and second switch control circuits adjust the on resistances of the first and second switch MOSFETs to be proportional to the resistances of first and second reference resistors, which have the same temperature coefficient as the resistors of which the divider network is composed. The on resistance of each of the first and second switch MOSFETs is equal to R.sub.ONi, and the resistance 2R' is equal to 2R-R.sub.ONi. The on resistances do not need to be binarily scaled.

Abstract: A digital-to-analog converter includes an input circuit (9) producing a plurality of corresponding switch control signals (25) in response to a digital input signal (D.sub.IN) and a resistive ladder network (10A) including an R/2R MSB ladder section (2) including a plurality of "R" resistors (17) and a plurality of "2R" resistors (5), and an R/2R LSB ladder section (3) including a plurality of "R" resistors (17) and a plurality of "2R" resistors (5). A scaling resistor (21) is coupled between a least significant node conductor (7-3) of the MSB ladder section and a most significant node conductor (7-4) of the LSB ladder section. A plurality of switch circuits (6) each selectively conducts a respective parallel resistor circuit (5) to a first reference voltage conductor (VREFH) or a second reference voltage conductor (VREFL) in response to the various switch control signals (25).

Abstract: A circuit for preventing analog-to-digital conversion errors due to MOS threshold shifts produced in a comparator during successive approximation testing of MSB and LSB groups of binarily weighted bit capacitors includes a first amplifier that amplifies voltage changes produced on a charge distribution conductor connected to the bit capacitors during successive approximation testing of the bit capacitors of the MSB group. The output of the first amplifier subjects a MOSFET in an input stage of the comparator to sufficiently large gate-to-source voltages to produce an MOS threshold shift in the MOSFET. During successive approximation testing of bit capacitors of the LSB group, a second amplifier amplifies signals representative of voltage changes produced on the charge distribution conductor and applies the amplified signals to the same MOSFET.

Abstract: In an analog-to-digital converter, a circuit for sampling an analog input signal that has a signal range above and below a ground reference voltage includes a divider circuit scaling the analog input signal down to a lower magnitude such that all values of the scaled analog input signal are above the ground reference voltage. The scaled down analog input signal is applied to a source electrode of a sampling MOSFET. A body-to-source voltage of the sampling MOSFET is maintained at approximately zero volts by applying the scaled down signal to a non-inverting input of a first operational amplifier and applying an output voltage produced by the first operational amplifier to its inverting input and a body electrode of the sampling MOSFET. A gate-to-source voltage of the sampling MOSFET is maintained at approximately 1.

Abstract: A dual successive approximation analog-to-digital converter, including circuitry for generating separate reference voltages for each analog-to-digital converter, is integrated onto a single semiconductor chip. A single successive approximation register including a 19 bit shift register and two 18 bit latches and associated gating circuitry operates to produce two sets of 18 successive approximation numbers, one supplied as successive digital inputs to a CDAC of one of the analog-to-digital converters and the other set of successive approximation numbers being applied as digital inputs to a CDAC of the other analog-to-digital converter. A CMOS comparator includes two high speed, low gain differential amplifier stages, the first including cascode MOSFETs to provide a high power supply rejection.

Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.

Abstract: A digital audio system for high-fidelity replication of wideband audio material. The system comprises a high-speed, low-noise and low-distortion, digital-to-analog converter including means for reducing spurious switching currents in the reconstructed audio signal. Such a converter is employed in both the encoding and decoding portions of the system.

Abstract: An integrated circuit digital-to-analog converter includes a nichrome feedback resistor having .+-.1% accuracy in its output amplifier, a plurality of bit current determining resistors that have .+-.30% manufacturing accuracy, a bias voltage circuit that produces a temperature-compensated bias voltage including an integrated potentiometer that is laser trimmed to compensate for the inaccuracy of the bit current determining resistors. The bit current determining resistors thereby produce constant, precise temperature-independent bit currents. The integrated potentiometer is accurately laser trimmed without changing the series resistance of the potentiometer. This prevents current density changes that change the temperature sensitivity of temperature-compensating elements in the bias voltage circuit.

Abstract: A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a push-pull output stage with only a pullup transistor and a pulldown transistor connected in series between the positive and negative supply voltages. The output stage includes circuitry that reduces the base voltage of the pullup transistor or pulldown transistor enough to reduce its collector current to near zero, greatly increasing its effective collector-to-emitter breakdown voltage.

Abstract: A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a circuit for external adjustment of the bit current of a particular bit of the digital-to-analog converter, which circuit produces a constant adjustment current that is summed with that bit current over a wide range of processing parameters and temperature, and requires only a single terminal for connection of an external potentiometer by means of which the bit current is adjusted and a small value filter capacitor for filtering out noise generated by an internal zener diode voltage reference circuit.

Abstract: A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes an input level shifting circuit that provides precise switching of a bit current switch circuit by producing a precise voltage drop across a level shifting resistor by drawing a current that is adjusted to compensate for variations in resistance of the level shifting resistors due to process parameter variations and temperature variations.

Abstract: In a digital to analog converter, a circuit for improving the performance of digital to analog converters by reducing and minimizing the variation in analog ground current is disclosed. The resulting digital to analog converter has reduced variation in output signal, the digital to analog converter can provide a more accurate representation of the input digital signal.

Abstract: A digital-to-analog converter circuit includes an open-loop reference circuit for regulating a plurality of bit switch currents and utilizes a high-speed single-ended input interface network for level shifting digital input signals to the bit switches whereat the level shifted input signals switch against a substantially fixed threshold voltage. The single-ended input interface network includes a PNP input transistor coupled to an input terminal and coupled by a resistor to a regulated voltage. The PNP input transistor is coupled to a level shifting network including an emitter follower transistor and a zener junction biased by a current source. The threshold voltage is also developed by a level shifting network that includes a zener junction for compensating variations within the level shifting network of the single-ended input interface network.

Abstract: An open-loop voltage reference circuit, adapted to regulate a plurality of bit switch currents within a digital-to-analog converter, includes a zener diode reference leg for developing a reference voltage. The reference leg also includes a base-emitter junction voltage multiplier for creating a compensating voltage having a temperature tracking coefficient that is equal and opposite to that of the zener diode junction voltage. The reference voltage developed by the reference leg is used to bias a temperature independent current within a slave leg, and a current mirror circuit mirrors the current within the slave leg for supplying a constant current to the reference leg. The magnitude of the reference voltage is reduced through a divider leg, and an emitter follower leg provides a low impedance bias voltage for driving the plurality of bit switch current sources.

Abstract: A system for automatically calibrating a main digital to analog converter (DAC) includes first and second adjustment DAC's, an offset DAC, a difference amplifier, an analog to digital converter (ADC), a microprocessor, and an analog switch. To calibrate the offset of the main DAC, the microprocessor causes "zeros" to be applied to the digital inputs of the main DAC and the offset DAC. The output of the offset DAC is coupled to an input of the difference amplifier. The microprocessor causes a ground voltage to be applied to the second input of the difference amplifier via the analog switch. The output of the difference amplifier is inputted to the ADC, which produces a first word. The first word is stored by the microprocessor. The analog switch is activated to apply the analog output voltage of the main DAC to the second input of the difference amplifier. The ADC produces a second word which is compared to the first word.