Patents by Inventor Jimmy S. Cheng

Jimmy S. Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for asynchronously stopping the clock in a processor
    Patent number: 5918043
    Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: June 29, 1999
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Tosaku Nakanishi, Jimmy S. Cheng
  • Computer system with power management feature for stopping the internal clock of a microprocessor
    Patent number: 5657483
    Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: August 12, 1997
    Inventors: James P. Kardach, Tosaku Nakanishi, Jimmy S. Cheng
  • Method of testing a microprocessor by masking of an internal clock signal
    Patent number: 5560002
    Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: September 24, 1996
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Tosaku Nakanishi, Jimmy S. Cheng
  • Method of operating a processor at a reduced speed
    Patent number: 5560001
    Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: September 24, 1996
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Tosaku Nakanishi, Jimmy S. Cheng
  • Method and apparatus for asynchronously stopping the clock in a processor
    Patent number: 5473767
    Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: December 5, 1995
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Tosaku Nakanishi, Jimmy S. Cheng