Abstract: A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

Abstract: A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).

Abstract: Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.

Abstract: Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.