Abstract: Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.

Abstract: Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

Abstract: A technique for improving performance of a data compression system is provided. The technique is applicable to compressed data sets that include compression blocks. Each compression block may be either compressed or uncompressed. Metadata indicating whether compression blocks are actually compressed or not is stored. If compression blocks are not compressed, then a read-decompress-modify-compress-write pipeline is bypassed. Instead, a compression unit writes the data specified by the partial request into the compression block, without reading, decompressing, modifying, recompressing, and writing the data, resulting in a much faster operation.

Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

Abstract: A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.

Abstract: A method and apparatus are described for controlling depth and power consumption of a first-in first-out (FIFO) memory including a data storage, a FIFO top register, a FIFO bottom register and control logic. The data storage may be segmented into a plurality of data storage segments. The FIFO top register may be configured to generate a first value indicating where a first entry in the data storage is stored. The FIFO bottom register may be configured to generate a second value indicating where a last entry in the data storage is stored. The control logic may be configured to determine which of the data storage segments to activate or deactivate based at least in part on the first and second values, and to monitor an available capacity and a write/read rate of the FIFO memory as data is read from and written to the activated data storage segments.

Abstract: A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.