Patents by Inventor Ji-Myung Na

Ji-Myung Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9537541
    Abstract: A method and electronic device for receiving information is provided. The method includes transmitting, by the electronic device, a scan time and an identification of the information to cause the identified information to be broadcast at the scan time; and scanning, by the electronic device, during the scan time to receive the information. The electronic device includes a transmitter configured to transmit a scan time and an identification of the information to cause the identified information to be broadcast at the scan time; and a scanner configured to scan during the scan time to receive the information.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 3, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jin-Yong Chung, Su-Hwan Kim, Tae-Sung Kim, Soo-Yong Kim, Ji-Myung Na
  • Patent number: 9515702
    Abstract: A demodulator for near field communication may include: a scale down circuit configured to receive first and second modulated signals from first and second power electrodes, and configured to provide a scale down signal to a first node by scaling down magnitudes of the first and second modulated signals; a current source coupled between the first node and a ground voltage, and configured to generate a constant current flowing from the first node to the ground voltage; a charge store circuit coupled between the first node and ground voltage, and configured to perform charge and discharge operations alternately, based on the scale down signal and constant current, to output an envelope signal, which corresponds to an envelope of the scale down signal; and/or an edge detector configured to generate input data, which correspond to the first and second modulated signals, based on a transition of the envelope signal.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Pil Cho, Ji-Myung Na, Il-jong Song
  • Patent number: 9436833
    Abstract: A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Myung Na, Kee-Moon Chun
  • Publication number: 20160218071
    Abstract: An integrated circuit includes a detector circuit including a sensor configured to sense an alteration to a physical characteristic of a substrate and to generate an alarm signal indicating such alteration and a circuit configured to respond to the generation of the alarm signal by implementing countermeasures. A smart card may include such a circuit to counteract a back side attack.
    Type: Application
    Filed: December 1, 2015
    Publication date: July 28, 2016
    Inventors: Ki-bum Nam, Ji-myung Na
  • Publication number: 20160134333
    Abstract: A demodulator for near field communication may include: a scale down circuit configured to receive first and second modulated signals from first and second power electrodes, and configured to provide a scale down signal to a first node by scaling down magnitudes of the first and second modulated signals; a current source coupled between the first node and a ground voltage, and configured to generate a constant current flowing from the first node to the ground voltage; a charge store circuit coupled between the first node and ground voltage, and configured to perform charge and discharge operations alternately, based on the scale down signal and constant current, to output an envelope signal, which corresponds to an envelope of the scale down signal; and/or an edge detector configured to generate input data, which correspond to the first and second modulated signals, based on a transition of the envelope signal.
    Type: Application
    Filed: June 16, 2015
    Publication date: May 12, 2016
    Inventors: Jong-Pil CHO, Ji-Myung NA, Il-jong SONG
  • Publication number: 20160065270
    Abstract: A method and electronic device for receiving information is provided. The method includes transmitting, by the electronic device, a scan time and an identification of the information to cause the identified information to be broadcast at the scan time; and scanning, by the electronic device, during the scan time to receive the information. The electronic device includes a transmitter configured to transmit a scan time and an identification of the information to cause the identified information to be broadcast at the scan time; and a scanner configured to scan during the scan time to receive the information.
    Type: Application
    Filed: July 22, 2015
    Publication date: March 3, 2016
    Inventors: Jin-Yong CHUNG, Su-Hwan KIM, Tae-Sung KIM, Soo-Yong KIM, Ji-Myung NA
  • Publication number: 20160034331
    Abstract: A memory system includes an abnormality detecting block including a plurality of abnormality detectors to detect whether an abnormal condition has occurred during a normal operation due to an external attack. An abnormality processing block is configured to process the abnormal condition in hardware, and a central processing unit is configured to execute a first process to detect whether the abnormal condition has occurred during the normal operation and to execute a second process to process the abnormal condition in software. A monitoring unit is configured to monitor an operation of the second process and to determine whether an error has occurred in the second process based on a monitoring result.
    Type: Application
    Filed: April 8, 2015
    Publication date: February 4, 2016
    Inventors: JI MYUNG NA, KI HONG KIM, KEE MOON CHUN
  • Publication number: 20150161401
    Abstract: A processor includes a security level determining unit and a variable pipeline. The security level determining unit determines a security level of first data to be processed by the processor. The variable pipeline receives the first data, generates original data by performing a decryption operation on the first data during a total number of one or more clock cycles corresponding to the security level determined by the security level determining unit, and processes the original data.
    Type: Application
    Filed: November 5, 2014
    Publication date: June 11, 2015
    Inventors: Ji-Myung NA, Ki-Hong KIM, Sang-Bum KIM, Jung-Hyun KIM
  • Publication number: 20150161416
    Abstract: A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal.
    Type: Application
    Filed: September 29, 2014
    Publication date: June 11, 2015
    Inventors: Ji-Myung NA, Kee-Moon CHUN
  • Patent number: 8561186
    Abstract: A detection circuit, including a sensing circuit configured to sense whether there is an external attack and generate second data from first data, a data conversion circuit configured to convert the first data to third data, and a comparator configured to compare the second data with the third data.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Myung Na, Jung Hyun Kim, Seong Il Park
  • Publication number: 20120117645
    Abstract: A detection circuit, including a sensing circuit configured to sense whether there is an external attack and generate second data from first data, a data conversion circuit configured to convert the first data to third data, and a comparator configured to compare the second data with the third data.
    Type: Application
    Filed: September 22, 2011
    Publication date: May 10, 2012
    Inventors: Ji Myung Na, Jung Hyun Kim, Seong Il Park
  • Patent number: 7748637
    Abstract: A smart card includes a plurality of function blocks, and a laser attack detector configured to detect an external laser attack on at least one of the plurality of function blocks. The laser attack detector may include a plurality of chain blocks connected in a chain configuration, and each of the chain blocks is configured to change the level of a detection value stored therein in response to an external laser attack.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Myung Na, Min-Kyu Kim
  • Publication number: 20080128516
    Abstract: A smart card includes a plurality of function blocks, and a laser attack detector configured to detect an external laser attack on at least one of the plurality of function blocks. The laser attack detector may include a plurality of chain blocks connected in a chain configuration, and each of the chain blocks is configured to change the level of a detection value stored therein in response to an external laser attack.
    Type: Application
    Filed: November 16, 2007
    Publication date: June 5, 2008
    Inventors: Ji-Myung Na, Min-Kyu Kim
  • Publication number: 20060219796
    Abstract: Example embodiments of present invention disclosed herein are directed to an IC chip card capable of detecting an external attack on data of a memory device. An IC chip card may include a memory device adapted to store data including a stored integrity identification value, an integrity identification value generating unit adapted to calculate an integrity identification value of the data, and a microprocessor adapted to compare the stored integrity identification value with the calculated integrity identification value to determine whether the data of the memory device has been compromised.
    Type: Application
    Filed: December 14, 2005
    Publication date: October 5, 2006
    Inventor: Ji-Myung Na