Patents by Inventor Jin-Bum Kim

Jin-Bum Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145541
    Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.
    Type: Application
    Filed: May 8, 2023
    Publication date: May 2, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Da Hye KIM, Jin Bum KIM, Gyeom KIM, Young Kwang KIM, Kyung Bin CHUN
  • Publication number: 20240131439
    Abstract: Provided is method of providing a conversation service in an electronic apparatus, including receiving a conversation input from a user terminal, identifying conversation history information associated with a user of the user terminal, obtaining score information corresponding to the user based on the conversation input and the conversation history information, obtaining response information based on the conversation input and the conversation history information, and providing the user terminal with at least one of the score information and the response information.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Hyperconnect LLC
    Inventors: Beom Su Kim, Su Hyun Lee, Sang Bum Kim, Enkhbayar Erdenee, Jin Yong Yoo, Min Chan Kim, Yeon Woo Lee
  • Patent number: 11953023
    Abstract: The present disclosure relates to a two-vane pump for wastewater and a design method of a two-vane pump for wastewater using machine learning, and more particularly, a design method of a two-vane pump using machine learning capable of having efficiency of a target head and performing optimal design for sizes of solids that can pass through and a two-vane pump for wastewater according to the machine learning.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 9, 2024
    Assignee: Korea Institute of Industrial Technology
    Inventors: Jin Hyuk Kim, Sung Kim, Sang Bum Ma
  • Publication number: 20240077973
    Abstract: A sensor device includes: a sensor panel including sensors arranged in a matrix form and sensor lines electrically connected to the sensors one-to-one; and a sensor driver configured to receive sensing signals from the sensors through the sensor lines, wherein the sensor driver is configured to simultaneously receive a first sensing signal from a first sensor using a first reference signal and a second sensing signal from a second sensor using a second reference signal, wherein the first reference signal and the second reference signal have a same waveform, a phase of the second reference signal is different from a phase of the first reference signal, and wherein a phase of the second sensing signal is different from a phase of the first sensing signal.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 7, 2024
    Inventors: Jin Woo KIM, Ja Seung KU, Chang Bum KIM, Dong Chun LEE
  • Patent number: 11915767
    Abstract: A negative voltage switching device includes a first switching circuit configured to transmit a first negative voltage, a second switching circuit configured to transmit a second negative voltage, and a switching selection circuit configured to select one of the first switching circuit or the second switching circuit for transmitting one of the first negative voltage and the second negative voltage to an output terminal.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: February 27, 2024
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jin Hyung Kim, Sung Bum Park, Kee Sik Ahn
  • Patent number: 11917881
    Abstract: A display device includes light transmitting areas including a first light transmitting area and light emitting areas around the light transmitting areas and including a first light emitting area disposed around the first light transmitting area, wherein the first light emitting area includes a first-first light emitting area adjacent to a first portion of each of the light transmitting areas, a first-second light emitting area adjacent to a second portion of each of the light transmitting areas, a first-third light emitting area adjacent to a third portion of each of the light transmitting areas, and a first-fourth light emitting area disposed adjacent to a fourth portion of each of the light transmitting areas. The first-first to first-fourth light emitting areas each include at least one of first to third light emitting portions to emit light of first to third colors, respectively.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woong Hee Jeong, Ki Bum Kim, Jin Yeong Kim, Hyang A Park, Tae Hoon Yang, Jong Chan Lee
  • Patent number: 11916171
    Abstract: A display device includes a substrate, a first electrode and a second electrode which are spaced apart from each other in a second direction, light-emitting elements spaced apart from each other in the first direction, a first contact electrode electrically contacting the light-emitting elements, and a second contact electrode electrically contacting the light-emitting elements. The first contact electrode electrically contacts the first electrode through a first contact portion disposed on the first electrode, the second contact electrode electrically contacts the second electrode through a second contact portion disposed on the second electrode, the first contact portion is disposed on an end portion in the first direction of the first contact electrode, and the second contact portion is disposed on an end portion in the first direction of the second contact electrode.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun Wook Lee, Ki Bum Kim, Jin Taek Kim, Jung Eun Hong
  • Publication number: 20240014304
    Abstract: A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of
    Type: Application
    Filed: February 16, 2023
    Publication date: January 11, 2024
    Inventors: Kyung Bin Chun, Jin Bum Kim, Dong Suk Shin, Gyeom Kim, Da Hye Kim
  • Publication number: 20240006409
    Abstract: There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.
    Type: Application
    Filed: April 25, 2023
    Publication date: January 4, 2024
    Inventors: Dong Woo KIM, Jin Bum KIM, Sang Moon LEE
  • Publication number: 20230420519
    Abstract: A semiconductor device having improved performance and reliability. The semiconductor device may include a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction. A plurality of gate structures may be on the lower pattern and spaced apart in the first direction, and a source/drain pattern, which may include a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. A liner recess that is defined by an inner surface of the semiconductor liner film may include a plurality of width extension regions, and a width of each width extension region in the first direction may increase and then decreases, as a distance increases in the second direction from an upper surface of the lower pattern.
    Type: Application
    Filed: February 17, 2023
    Publication date: December 28, 2023
    Inventors: Da Hye Kim, Gyeom Kim, Jin Bum Kim, Su Jin Jung, Kyung Bin Chun
  • Publication number: 20230411529
    Abstract: A semiconductor device includes a lower pattern extending in a first direction, a first blocking structure which is on the lower pattern and includes at least one first blocking film comprising an oxygen-doped crystalline silicon film, a source/drain pattern on the first blocking structure, and a gate structure which extends in a second direction on the lower pattern and includes a gate electrode and a gate insulating film. Related fabrication methods are also discussed.
    Type: Application
    Filed: January 26, 2023
    Publication date: December 21, 2023
    Inventors: Hyo Jin Kim, Sang Moon Lee, Jin Bum Kim, Yong Jun Nam
  • Publication number: 20230395668
    Abstract: A semiconductor device includes a substrate; an active pattern disposed on the substrate and extending in a first direction; a plurality of gate structures, wherein the plurality of gate structures is disposed on the active pattern and arranged in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and wherein the gate electrode extends in a second direction; a source/drain pattern disposed between adjacent gate structures of the plurality of gate structures; a source/drain contact connected to the source/drain pattern; and a contact silicide film disposed between the source/drain pattern and the source/drain contact, wherein the contact silicide film includes a bowl region that wraps a lower portion of the source/drain contact, and a protruding region that protrudes from the bowl region of the contact silicide film.
    Type: Application
    Filed: April 5, 2023
    Publication date: December 7, 2023
    Inventors: Su Jin JUNG, Jin Bum KIM, In Gyu JANG
  • Publication number: 20230317849
    Abstract: A semiconductor device includes a lower pattern extending in a first direction, and protruding from a substrate in a second direction, a lower insulating pattern on the lower pattern, and in contact with an upper surface of the lower pattern, a channel pattern on the lower insulating pattern, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and a source/drain pattern disposed on the lower pattern, and connected to the channel pattern. A vertical level of a lowermost portion of the source/drain pattern is lower than a vertical level of a bottom surface of the lower insulating pattern. The gate electrode overlaps the lower insulating pattern in the second direction.
    Type: Application
    Filed: October 7, 2022
    Publication date: October 5, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum KIM, Hyo Jin KIM, Yong Jun NAM, Sang Moon LEE, Dong Woo KIM, In Geon HWANG
  • Patent number: 11735663
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
  • Patent number: 11705503
    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 18, 2023
    Inventors: Jin Bum Kim, MunHyeon Kim, Hyoung Sub Kim, Tae Jin Park, Kwan Heum Lee, Chang Woo Noh, Maria Toledano Lu Que, Hong Bae Park, Si Hyung Lee, Sung Man Whang
  • Publication number: 20230214226
    Abstract: The present invention relates to an edge cloud infrastructure building technology, and particularly, to a system and a method for building an edge cloud, which can simultaneously a large-scale edge cloud in parallel.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 6, 2023
    Inventors: Jin Bum KIM, JI SEOK JEONG
  • Publication number: 20230214202
    Abstract: The present invention relates to an installation technology of components of an edge cloud, and particularly, to a system and a method of edge cloud building for high-speed installation of components of an edge cloud, which can reduce generation and setting operation hours of individual components by automating installation of individual components of the edge cloud. To this end, in the edge cloud building system according to the present invention as a edge cloud building system for high-speed installation of components of an edge cloud, hierarchical components (IaaS, KaaS, PaaS) of an edge cloud are installed by using a server node image and a PaaS component image, and then detailed setting of the hierarchical components is performed by using a declarative script.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 6, 2023
    Inventors: Jin Bum KIM, DONG MUK LEE
  • Publication number: 20230011153
    Abstract: A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source/drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source/drain contact electrically connected to, and on, the source/drain region, and a silicide layer between the source/drain region and the source/drain contact which contacts contact with the second doping layer and extends to an upper surface of the source/drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.
    Type: Application
    Filed: February 15, 2022
    Publication date: January 12, 2023
    Inventors: Dong Woo Kim, Gyeom Kim, Jin Bum Kim, Dong Suk Shin, Sang Moon Lee
  • Publication number: 20220415905
    Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 29, 2022
    Inventors: Jin-Bum KIM, Myung-Gil KANG, Kang-Hun MOON, Cho-Eun LEE, Su-Jin JUNG, Min-Hee CHOI, Yang XU, Dong-Suk SHIN, Kwan-Heum LEE, Hoi-Sung CHUNG
  • Patent number: D1021689
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 9, 2024
    Assignee: NEUBILITY
    Inventors: Sang Min Lee, Hyun Gon Kim, Ki Joon Seong, Jin Bum Kim