Abstract: A display device includes a substrate, a first electrode and a second electrode which are spaced apart from each other in a second direction, light-emitting elements spaced apart from each other in the first direction, a first contact electrode electrically contacting the light-emitting elements, and a second contact electrode electrically contacting the light-emitting elements. The first contact electrode electrically contacts the first electrode through a first contact portion disposed on the first electrode, the second contact electrode electrically contacts the second electrode through a second contact portion disposed on the second electrode, the first contact portion is disposed on an end portion in the first direction of the first contact electrode, and the second contact portion is disposed on an end portion in the first direction of the second contact electrode.

Abstract: A semiconductor device includes a lower pattern extending in a first direction, a plurality of wire patterns spaced apart from the lower pattern in a second direction on the lower pattern, and a gate electrode surrounding the plurality of wire patterns and extending in a third direction, on the lower pattern. Each of the plurality of wire patterns includes a transition metal dichalcogenide (TMD) material. Each of the plurality of wire patterns includes a pair of first areas protruding from sidewalls of the gate electrode in the first direction and a second area between the first areas. A phase of the first area is different from a phase of the second area.

Abstract: A semiconductor device includes: a substrate, an active pattern extending in a first horizontal direction on the substrate, a plurality of nanosheets spaced apart from each other and stacked in a vertical direction on the active pattern, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region disposed on at least one side of the gate electrode on the active pattern, the source/drain region including a first layer doped with a metal, and a second layer disposed on the first layer, and an inner spacer disposed between the gate electrode and the first layer, between each of the plurality of nanosheets, the inner spacer in contact with the first layer, the inner spacer including a metal oxide formed by oxidizing the same material as the metal.

Abstract: A display device including: a substrate; a conductive layer on the substrate and including a first voltage line and a second voltage line extending in a first direction; a first electrode and a second electrode on the conductive layer, extending in the first direction, and spaced apart from each other; a plurality of light-emitting elements on the first electrode and the second electrode; and an electrode pattern on the conductive layer and separated from the first electrode. The electrode pattern overlaps the first voltage line in a thickness direction and directly contacts the first voltage line.

Abstract: A pixel includes a first insulating film disposed on a substrate, a light emitting element disposed on the first insulating film, a second insulating film disposed on the light emitting element to cover at least a portion of the light emitting element, a first contact electrode and a second contact electrode, each of the first and second contact electrodes including at least a portion disposed on the first insulating film and connected to the light emitting element, and an encapsulation layer including a photosensitive material.

Abstract: A 5th Generation (5G) or pre-5G communication system for supporting higher data transmission rates beyond 4th Generation (4G) communication systems such as long term evolution (LTE) systems. A method for transmitting download control information in a communication system is provided. The method includes configuring the control information indicating at least one control channel element (CCE) including at least one resource element group (REG) unit interleaved based on the interleaving information indicated by a higher layer signaling; and transmitting, to a user equipment (UE), the configured control information.

Abstract: A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

Abstract: The present application can provide a curable composition capable of securing processability due to excellent blending properties with a filler while having little viscosity change with time and for forming a cured product having excellent electrical insulation performance, and can provide a device comprising, between an exothermic element and a cooling region, a cured product of a tow-component curable composition including the curable composition in thermal contact with both.

Abstract: A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including a first side and a second side opposite to the first side; an active pattern that is on the first side and extends in a first direction; an etch stop layer that extends along the first side of the substrate and does not extend along side faces of the active pattern; a field insulating film that is on the first side and covers at least a part of the side faces of the active pattern; a gate structure that extends in a second direction intersecting the first direction on the active pattern and the field insulating film; a through contact that extends in a third direction intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer; a buried pattern connected to the through contact, inside the substrate; and a backside wiring structure that is on the second side and electrically connected to the buried pattern.

Abstract: A battery pack includes a battery cell stack formed by a plurality of stacked battery cells, a battery module housing configured to wrap the other outer surfaces of the battery cell stack excluding a first surface and a second surface, from which electrode leads protrude, a water tank configured to supply a coolant to the battery cell or the battery module housing, and a battery pack case configured to receive a plurality of battery module housings. The battery pack case includes a pack case space portion located adjacent to the first surface and a crossbeam located adjacent to the second surface, whereby, when fire breaks out in the battery cell, it is possible to rapidly and accurately prevent spread of flames of the ignited battery cell.

Abstract: A method for manufacturing a semiconductor device includes providing a buffer substrate, forming a sacrificial contact film on the buffer substrate, forming a sacrificial contact pattern by patterning the sacrificial contact film, forming a first base layer on the buffer substrate that surrounds the sacrificial contact pattern, forming an active pattern on the first base layer and the sacrificial contact pattern that extends in a first direction, forming a gate electrode on the active pattern extending in a second direction intersecting the first direction, forming a source/drain pattern on a side surface of the gate electrode for connection to the active pattern. The source/drain pattern overlaps the sacrificial contact pattern in a third direction intersecting the first and second directions. The sacrificial contact pattern is exposed by removing the buffer substrate. A lower source/drain contact is formed for connection to the source/drain pattern by replacing the exposed sacrificial contact pattern.

Abstract: Provided is a distributed and associative container platform system which has an advantage of providing flexible movement of services and infinite extension of computing resources by interconnecting regionally distributed multiple container platforms and enhancing security.

Abstract: A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern; a gate structure disposed on the lower pattern; and a source/drain pattern disposed on the lower pattern, and connected to each of the plurality of sheet patterns, wherein the plurality of sheet patterns include a first sheet pattern and a second sheet pattern. The second sheet pattern is disposed between the first sheet pattern and the lower pattern. A first upper width of an upper surface of the first sheet pattern is greater than a first lower width of a bottom surface of the first sheet pattern, and a second upper width of an upper surface of the second sheet pattern is smaller than a second lower width of a bottom surface of the second sheet pattern.

Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.

Abstract: A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of

Abstract: There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.

Abstract: A semiconductor device having improved performance and reliability. The semiconductor device may include a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction. A plurality of gate structures may be on the lower pattern and spaced apart in the first direction, and a source/drain pattern, which may include a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. A liner recess that is defined by an inner surface of the semiconductor liner film may include a plurality of width extension regions, and a width of each width extension region in the first direction may increase and then decreases, as a distance increases in the second direction from an upper surface of the lower pattern.