Patents by Inventor Jin-Bum Kim

Jin-Bum Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12149353
    Abstract: A 5th Generation (5G) or pre-5G communication system for supporting higher data transmission rates beyond 4th Generation (4G) communication systems such as long term evolution (LTE) systems. A method for transmitting download control information in a communication system is provided. The method includes configuring the control information indicating at least one control channel element (CCE) including at least one resource element group (REG) unit interleaved based on the interleaving information indicated by a higher layer signaling; and transmitting, to a user equipment (UE), the configured control information.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: November 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyoung Kim, Young-Bum Kim, Jin-Young Oh, Seung-Hoon Choi, Tae-Han Bae
  • Publication number: 20240363712
    Abstract: A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.
    Type: Application
    Filed: November 9, 2023
    Publication date: October 31, 2024
    Inventors: Sang Moon Lee, Jin Bum Kim, Hyo Jin Kim, Yong Jun Nam, In Geon Hwang
  • Publication number: 20240301267
    Abstract: The present application can provide a curable composition capable of securing processability due to excellent blending properties with a filler while having little viscosity change with time and for forming a cured product having excellent electrical insulation performance, and can provide a device comprising, between an exothermic element and a cooling region, a cured product of a tow-component curable composition including the curable composition in thermal contact with both.
    Type: Application
    Filed: January 26, 2022
    Publication date: September 12, 2024
    Applicants: LG Chem, Ltd., LG Chem, Ltd.
    Inventors: Sol Yi Lee, Je Sik Jung, Hyoung Sook Park, Jin Hyeok Won, Hye Jin Kim, Sung Bum Hong, Jong Hun Choi, Sang Hyuk Seo, Jae Min Jung
  • Patent number: 12068042
    Abstract: A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 20, 2024
    Assignee: SK keyfoundry Inc.
    Inventors: Jin Hyung Kim, Sung Bum Park, Kee Sik Ahn
  • Publication number: 20240266288
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including a first side and a second side opposite to the first side; an active pattern that is on the first side and extends in a first direction; an etch stop layer that extends along the first side of the substrate and does not extend along side faces of the active pattern; a field insulating film that is on the first side and covers at least a part of the side faces of the active pattern; a gate structure that extends in a second direction intersecting the first direction on the active pattern and the field insulating film; a through contact that extends in a third direction intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer; a buried pattern connected to the through contact, inside the substrate; and a backside wiring structure that is on the second side and electrically connected to the buried pattern.
    Type: Application
    Filed: September 13, 2023
    Publication date: August 8, 2024
    Inventor: Jin Bum KIM
  • Patent number: 12057597
    Abstract: A battery pack includes a battery cell stack formed by a plurality of stacked battery cells, a battery module housing configured to wrap the other outer surfaces of the battery cell stack excluding a first surface and a second surface, from which electrode leads protrude, a water tank configured to supply a coolant to the battery cell or the battery module housing, and a battery pack case configured to receive a plurality of battery module housings. The battery pack case includes a pack case space portion located adjacent to the first surface and a crossbeam located adjacent to the second surface, whereby, when fire breaks out in the battery cell, it is possible to rapidly and accurately prevent spread of flames of the ignited battery cell.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: August 6, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Jin Yong Park, Young Bum Cho, Jeong Oh Moon, Hyeon Ki Yun, Eun Gyu Shin, Ho June Chi, Kyung Woo Kim
  • Publication number: 20240258176
    Abstract: A method for manufacturing a semiconductor device includes providing a buffer substrate, forming a sacrificial contact film on the buffer substrate, forming a sacrificial contact pattern by patterning the sacrificial contact film, forming a first base layer on the buffer substrate that surrounds the sacrificial contact pattern, forming an active pattern on the first base layer and the sacrificial contact pattern that extends in a first direction, forming a gate electrode on the active pattern extending in a second direction intersecting the first direction, forming a source/drain pattern on a side surface of the gate electrode for connection to the active pattern. The source/drain pattern overlaps the sacrificial contact pattern in a third direction intersecting the first and second directions. The sacrificial contact pattern is exposed by removing the buffer substrate. A lower source/drain contact is formed for connection to the source/drain pattern by replacing the exposed sacrificial contact pattern.
    Type: Application
    Filed: September 18, 2023
    Publication date: August 1, 2024
    Inventors: Jin Bum KIM, Sang Moon Lee
  • Patent number: 12026538
    Abstract: Provided is a distributed and associative container platform system which has an advantage of providing flexible movement of services and infinite extension of computing resources by interconnecting regionally distributed multiple container platforms and enhancing security.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 2, 2024
    Assignees: ACORNSOFT CO., LTD.
    Inventor: Jin Bum Kim
  • Publication number: 20240153991
    Abstract: A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern; a gate structure disposed on the lower pattern; and a source/drain pattern disposed on the lower pattern, and connected to each of the plurality of sheet patterns, wherein the plurality of sheet patterns include a first sheet pattern and a second sheet pattern. The second sheet pattern is disposed between the first sheet pattern and the lower pattern. A first upper width of an upper surface of the first sheet pattern is greater than a first lower width of a bottom surface of the first sheet pattern, and a second upper width of an upper surface of the second sheet pattern is smaller than a second lower width of a bottom surface of the second sheet pattern.
    Type: Application
    Filed: August 2, 2023
    Publication date: May 9, 2024
    Inventors: Gyeom KIM, Da Hye KIM, Young Kwang KIM, Jin Bum KIM, Kyung Bin CHUN
  • Publication number: 20240145541
    Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.
    Type: Application
    Filed: May 8, 2023
    Publication date: May 2, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Da Hye KIM, Jin Bum KIM, Gyeom KIM, Young Kwang KIM, Kyung Bin CHUN
  • Publication number: 20240014304
    Abstract: A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of
    Type: Application
    Filed: February 16, 2023
    Publication date: January 11, 2024
    Inventors: Kyung Bin Chun, Jin Bum Kim, Dong Suk Shin, Gyeom Kim, Da Hye Kim
  • Publication number: 20240006409
    Abstract: There is provided a semiconductor device including an active pattern which includes a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on a substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a capping pattern being in contact with the protruding pattern on the protruding pattern, a first gate structure and a second gate structure which are disposed on the lower pattern and spaced apart from each other in the first direction, and a source/drain pattern which is disposed on the lower pattern and in contact with the sheet pattern, wherein a thickness of the capping pattern in a portion that overlaps the first gate structure is different from a thickness of the capping pattern in a portion that overlaps the second gate structure.
    Type: Application
    Filed: April 25, 2023
    Publication date: January 4, 2024
    Inventors: Dong Woo KIM, Jin Bum KIM, Sang Moon LEE
  • Publication number: 20230420519
    Abstract: A semiconductor device having improved performance and reliability. The semiconductor device may include a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction. A plurality of gate structures may be on the lower pattern and spaced apart in the first direction, and a source/drain pattern, which may include a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. A liner recess that is defined by an inner surface of the semiconductor liner film may include a plurality of width extension regions, and a width of each width extension region in the first direction may increase and then decreases, as a distance increases in the second direction from an upper surface of the lower pattern.
    Type: Application
    Filed: February 17, 2023
    Publication date: December 28, 2023
    Inventors: Da Hye Kim, Gyeom Kim, Jin Bum Kim, Su Jin Jung, Kyung Bin Chun
  • Publication number: 20230411529
    Abstract: A semiconductor device includes a lower pattern extending in a first direction, a first blocking structure which is on the lower pattern and includes at least one first blocking film comprising an oxygen-doped crystalline silicon film, a source/drain pattern on the first blocking structure, and a gate structure which extends in a second direction on the lower pattern and includes a gate electrode and a gate insulating film. Related fabrication methods are also discussed.
    Type: Application
    Filed: January 26, 2023
    Publication date: December 21, 2023
    Inventors: Hyo Jin Kim, Sang Moon Lee, Jin Bum Kim, Yong Jun Nam
  • Publication number: 20230395668
    Abstract: A semiconductor device includes a substrate; an active pattern disposed on the substrate and extending in a first direction; a plurality of gate structures, wherein the plurality of gate structures is disposed on the active pattern and arranged in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and wherein the gate electrode extends in a second direction; a source/drain pattern disposed between adjacent gate structures of the plurality of gate structures; a source/drain contact connected to the source/drain pattern; and a contact silicide film disposed between the source/drain pattern and the source/drain contact, wherein the contact silicide film includes a bowl region that wraps a lower portion of the source/drain contact, and a protruding region that protrudes from the bowl region of the contact silicide film.
    Type: Application
    Filed: April 5, 2023
    Publication date: December 7, 2023
    Inventors: Su Jin JUNG, Jin Bum KIM, In Gyu JANG
  • Publication number: 20230317849
    Abstract: A semiconductor device includes a lower pattern extending in a first direction, and protruding from a substrate in a second direction, a lower insulating pattern on the lower pattern, and in contact with an upper surface of the lower pattern, a channel pattern on the lower insulating pattern, a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction, wherein each of the plurality of gate structures includes a gate electrode and a gate insulating film, and a source/drain pattern disposed on the lower pattern, and connected to the channel pattern. A vertical level of a lowermost portion of the source/drain pattern is lower than a vertical level of a bottom surface of the lower insulating pattern. The gate electrode overlaps the lower insulating pattern in the second direction.
    Type: Application
    Filed: October 7, 2022
    Publication date: October 5, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum KIM, Hyo Jin KIM, Yong Jun NAM, Sang Moon LEE, Dong Woo KIM, In Geon HWANG
  • Patent number: 11735663
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
  • Patent number: 11705503
    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 18, 2023
    Inventors: Jin Bum Kim, MunHyeon Kim, Hyoung Sub Kim, Tae Jin Park, Kwan Heum Lee, Chang Woo Noh, Maria Toledano Lu Que, Hong Bae Park, Si Hyung Lee, Sung Man Whang
  • Patent number: D1021689
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 9, 2024
    Assignee: NEUBILITY
    Inventors: Sang Min Lee, Hyun Gon Kim, Ki Joon Seong, Jin Bum Kim
  • Patent number: D1026732
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 14, 2024
    Assignee: NEUBILITY
    Inventors: Sang Min Lee, Hyun Gon Kim, Ki Joon Seong, Jin Bum Kim