Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor including a pair of first source/drain regions and a plurality of stacked first channels extending in the first lateral direction between the pair of first source/drain regions. The CFET includes a second transistor above the first transistor and including a pair of second source/drain regions and a plurality of stacked second channels extending in the first lateral direction between the pair of second source/drain regions. The CFET includes gate spacer layers defining a gate trench adjacent to the second channels and a gate metal in the gate trench and between the second channels. The gate metal has a first length in the first lateral direction in the gate trench and a second length in the first lateral direction between the second channels. The first length is greater than the second length.

Abstract: Disclosed in the present application are an operating method for a memory controller, a memory controller, a system, and an electronic device. The operating method can include, when detecting that remaining capacity of a used backup area in the memory is less than capacity required for redundancy check data to be written, determining a backup area to be used from the memory, determining valid redundancy check data belonging to garbage collection in the used backup area, and backing up the valid redundancy check data into the backup area to be used, and erasing the used backup area.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an isolation structure formed over the substrate. The semiconductor structure includes a gate structure formed on the nanostructures, and the gate structure includes a gate dielectric layer and a metal layer over the gate dielectric layer. The semiconductor structure includes a first gate spacer layer formed on a sidewall of the gate structure, and a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the first gate spacer layer. The gate structure includes a first portion on the isolation structure and a second portion below a topmost nanostructure, and the first portion has a first gate length, the second portion has a second gate length, and the first gate length is greater than the second gate length.

Abstract: This application discloses a redox complex and preparation method therefor and use thereof. The redox complex contains a bridged 2,2?-biimidazole structure, through bridging two nitrogen atoms with active hydrogen, stabilizing the structure of the imidazole ring, preventing conformational isomerism of the 2,2?-biimidazole. When the bridged 2,2?-biimidazole structure coordinates with transition metals to form a complex, which significantly improves the efficiency and stability of the complex. Therefore, when the redox complex is used as the electron mediator in sensors, it exhibits a lower oxidation potential, while significantly extending the service life of the sensors.

Abstract: A semiconductor structure includes a substrate, a plurality of active channels vertically stacked to each other, a first dielectric layer in the topmost active channel, and a first oxide layer in the topmost active channel and includes a first lateral oxide portion connected with the first dielectric layer. The first lateral oxide portion has a thickness greater than that of the first dielectric layer due to an ox-oxidation.

Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. The method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. The first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. The method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

Abstract: A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

Abstract: A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: epitaxially growing a semiconductor material among at least two channel layers; implanting pnictogen dopants in the semiconductor material; implanting chalcogen dopants in the semiconductor material; annealing the semiconductor material with the chalcogen dopants; forming a bottom contact etching stop layer (BCESL) on the semiconductor material with the chalcogen dopants; and etching the BCESL and forming a metal layer above the semiconductor material.

Abstract: A device includes a bottom transistor and a top transistor over the bottom transistor to form a complementary field effect transistor. The bottom transistor includes an active channel layer, a floating channel layer, a gate structure, a first source/drain epitaxial structure, and a second source/drain epitaxial structure. The floating channel layer is over the active channel layer. The gate structure wraps around the active channel layer and the floating channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are connected to the active channel layer and spaced apart from the floating channel layer.

Abstract: Embodiments of the present disclosure provide a GAA device fabricated from a substrate having a (551)<110> top surface. Selecting the (551)/<110> substrate enables channel height scaling with improved hole mobility and without sacrificing electron mobility.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The method includes the following steps. A plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate are formed. The second semiconductor layers are removed to form openings between the first semiconductor layers. A plurality of gate dielectric layers is formed, and each of the gate dielectric layers surrounds one of the first semiconductor layers respectively. A plurality of floating gate layers is formed, wherein the floating gate layers are electrically connected to each other and surround the gate dielectric layers respectively, and the gate dielectric layers are located between the first semiconductor layers and the floating gate layers respectively.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a first stack over a substrate and a second stack over the first stack. The first stack includes semiconductor layers interleaved by dielectric layers. The second stack includes channel layers interleaved by sacrificial layers. The method also includes patterning the second stack to form a fin-shape structure, recessing a portion of the fin-shape structure to form a recess exposing a top surface of the first stack, epitaxially growing an epitaxial feature directly from the top surface of the first stack, removing the sacrificial layers to release the channel layers, and forming a gate structure wrapping around each of the channel layers.

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

Abstract: A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

Abstract: A device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of first semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Abstract: The present application discloses example operating methods for memory controllers, memory controllers, systems, and electronic devices. The operating methods include: in response to a working mode switching command, determining redundancy check data in a cache of a memory controller, the redundancy check data to be used for data recovery of a storage area in a memory array; and sending, to a memory device, a write command to cause writing of the redundancy check data into a backup area of the memory array. Other examples are described.