Abstract: A semiconductor structure is provided. The semiconductor structure includes first nanostructures over a first region of a substrate, a first gate stack surrounding the first nanostructures, and a first gate spacer layer alongside the first gate stack. One of the first nanostructures includes an end portion surrounded by the first gate spacer layer, and the end portion of the one of the first nanostructures has a first boron concentration. The semiconductor structure further includes second nanostructures over a second region of the substrate, a second gate stack surrounding the second nanostructures, and a second gate spacer layer alongside the second gate stack. One of the second nanostructures includes an end portion surrounded by the second gate spacer layer, and the end portion of the one of the second nanostructures has a second boron concentration that is less than the first boron concentration.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure in a first p-type device region and a second fin structure in a second p-type device region. Each of the first fin structure and the second fin structure includes alternatingly stacking first semiconductor layers and second semiconductor layers. The method also includes etching the first fin structure and the second fin structure to form a first recess and a second recess, respectively, forming a first patterned mask layer to cover the second p-type device region, laterally recessing the second semiconductor layers of the first fin structure to form first notches, removing the first patterned mask layer, forming a first p-type source/drain feature in the first recess and the notches, and forming a second p-type source/drain feature in the second recess.

Abstract: A method includes forming a complementary Field-Effect Transistor (CFET) including a first FinFET and a second FinFET. The processes for forming the first FinFET includes forming at least one semiconductor fin having a first total count, and forming a first gate stack on the at least one semiconductor fin. The second FinFET is vertically aligned to the first FinFET. The processes for forming the second FinFET includes forming a plurality of semiconductor fins, wherein the plurality of semiconductor fins have a second total count greater than the first total count, and forming a second gate stack on the plurality of semiconductor fins.

Abstract: An object management method, an electronic device and a storage medium are provided. The method includes: obtaining, in response to creating a first object combination on a management page of a target entity, at least two parent objects included in the first object combination, where the at least two parent objects belong to the target entity; obtaining a target child object corresponding to each of the at least two parent objects from sub-entities of the target entity, where attribute information of the target child object is the same as attribute information of the corresponding parent object; and displaying, for a first sub-entity including at least two target child objects among the sub-entities of the target entity, a second object combination on a management page of the first sub-entity, where the second object combination includes the at least two target child objects.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first fin segment and a second fin segment over a substrate. The first fin segment includes a first sidewall and a second sidewall opposite to the first sidewall. The second fin segment includes a third sidewall and a fourth sidewall opposite to the third sidewall. In a plan view, the first sidewall of the first fin segment is between the third sidewall and the fourth sidewall of the second fin segment. The semiconductor structure further includes a first gate stack extending in a first direction across the first fin segment, a second gate stack extending in the first direction across the second fin segment, and a dielectric layer extending in the first direction between the first fin segment and the second fin segment.

Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

Abstract: There are a mesh-shaped porous CO2-capturing solution and a separation method for CO2 gas. The composition of the capturing solution has 1%-50% of a specific chemical agent and 50%-99% of water. The specific chemical agent is one or a combination of two or more of an imidazole substance, an imidazole ionic liquid, a piperazine substance, and an amino alcohol substance. The mesh-shaped porous CO2-capturing solution remains stable and adsorbs CO2 at low temperatures. The porous structure disintegrates and releases CO2 at high temperatures. The mesh-shaped porous CO2-capturing solution has advantages, including fast absorption rate, a large absorption capacity, and a low regeneration temperature.

Abstract: A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor including a pair of first source/drain regions and a plurality of stacked first channels extending in the first lateral direction between the pair of first source/drain regions. The CFET includes a second transistor above the first transistor and including a pair of second source/drain regions and a plurality of stacked second channels extending in the first lateral direction between the pair of second source/drain regions. The CFET includes gate spacer layers defining a gate trench adjacent to the second channels and a gate metal in the gate trench and between the second channels. The gate metal has a first length in the first lateral direction in the gate trench and a second length in the first lateral direction between the second channels. The first length is greater than the second length.

Abstract: Disclosed in the present application are an operating method for a memory controller, a memory controller, a system, and an electronic device. The operating method can include, when detecting that remaining capacity of a used backup area in the memory is less than capacity required for redundancy check data to be written, determining a backup area to be used from the memory, determining valid redundancy check data belonging to garbage collection in the used backup area, and backing up the valid redundancy check data into the backup area to be used, and erasing the used backup area.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and an isolation structure formed over the substrate. The semiconductor structure includes a gate structure formed on the nanostructures, and the gate structure includes a gate dielectric layer and a metal layer over the gate dielectric layer. The semiconductor structure includes a first gate spacer layer formed on a sidewall of the gate structure, and a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the first gate spacer layer. The gate structure includes a first portion on the isolation structure and a second portion below a topmost nanostructure, and the first portion has a first gate length, the second portion has a second gate length, and the first gate length is greater than the second gate length.

Abstract: This application discloses a redox complex and preparation method therefor and use thereof. The redox complex contains a bridged 2,2?-biimidazole structure, through bridging two nitrogen atoms with active hydrogen, stabilizing the structure of the imidazole ring, preventing conformational isomerism of the 2,2?-biimidazole. When the bridged 2,2?-biimidazole structure coordinates with transition metals to form a complex, which significantly improves the efficiency and stability of the complex. Therefore, when the redox complex is used as the electron mediator in sensors, it exhibits a lower oxidation potential, while significantly extending the service life of the sensors.

Abstract: A semiconductor structure includes a substrate, a plurality of active channels vertically stacked to each other, a first dielectric layer in the topmost active channel, and a first oxide layer in the topmost active channel and includes a first lateral oxide portion connected with the first dielectric layer. The first lateral oxide portion has a thickness greater than that of the first dielectric layer due to an ox-oxidation.

Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. The method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. The first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. The method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

Abstract: A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

Abstract: A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.