Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure in a first p-type device region and a second fin structure in a second p-type device region. Each of the first fin structure and the second fin structure includes alternatingly stacking first semiconductor layers and second semiconductor layers. The method also includes etching the first fin structure and the second fin structure to form a first recess and a second recess, respectively, forming a first patterned mask layer to cover the second p-type device region, laterally recessing the second semiconductor layers of the first fin structure to form first notches, removing the first patterned mask layer, forming a first p-type source/drain feature in the first recess and the notches, and forming a second p-type source/drain feature in the second recess.

Abstract: A semiconductor device includes semiconductor nanosheets, a gate structure, and a dielectric spacer. The semiconductor nanosheets are vertically stacked over each other, disposed above a semiconductor substrate, and serve as channel regions. A bottommost semiconductor nanosheet most proximate from the semiconductor substrate is a thinnest nanosheet of the semiconductor nanosheets. The gate structure surrounds each of the semiconductor nanosheets in a first cross-section, and the dielectric spacer is interposed between the bottommost semiconductor nanosheet and the semiconductor substrate and adjoins the gate structure in the first cross-section.

Abstract: An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.

Abstract: A capacitive wireless power transfer coupler, includes: a coupler transmitting side, including two electrode plates arranged in a same plane, a shielding plate parallel to the electrode plates, and a filling dielectric between each of the electrode plates and the shielding plate; a coupler receiving side, having a same structure as the coupler transmitting side. A side provided with the electrode plates of the coupler transmitting side faces a side provided with the electrode plates of the coupler receiving side, and power transfer is achieved between the two sides through a transfer dielectric, where a relative dielectric constant of the filling dielectric is less than a relative dielectric constant of the transfer dielectric. The issues of increased coupler volume, limited improvement in the capacitive coupling coefficient, and low efficiency of power transfer of the existing capacitive coupler, can be solved.

Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Abstract: A capacitive wireless power transfer coupler, includes: a coupler transmitting side, including two electrode plates arranged in a same plane, a shielding plate parallel to the electrode plates, and a filling dielectric between each of the electrode plates and the shielding plate; a coupler receiving side, having a same structure as the coupler transmitting side. A side provided with the electrode plates of the coupler transmitting side faces a side provided with the electrode plates of the coupler receiving side, and power transfer is achieved between the two sides through a transfer dielectric, where a relative dielectric constant of the filling dielectric is less than a relative dielectric constant of the transfer dielectric. The issues of increased coupler volume, limited improvement in the capacitive coupling coefficient, and low efficiency of power transfer of the existing capacitive coupler, can be solved.

Abstract: The present disclosure is directed to an operating method of a memory controller, a memory controller, a memory system, and an electronic device. Herein, the operating method can include determining a backup region to be used in an idle state from a memory array, when detecting that remaining capacity of a currently used backup region for storing redundancy parity data in the memory array is less than a required capacity of redundancy parity data to be written, determining the quantity of all backup regions for storing redundancy parity data including the backup region to be used in the memory array, deciding whether the quantity is larger than a preset threshold, and erasing backup regions having stored redundancy parity data in the memory array when the quantity is larger than the preset threshold.

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Abstract: A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

Abstract: The present application relates to a regulator containing a tricyclic derivative, a preparation method therefor and an application thereof, and in particular to a compound represented by general formula (Ia), a preparation method therefor and a pharmaceutical composition containing the compound, and an application thereof in the preparation of drugs for preventing and/or treating central nervous system diseases and/or peripheral diseases related to mammalian 5-hydroxytryptamine and/or dopamine and/or norepinephrine neurotransmitter transmission.

Abstract: A semiconductor structure includes a channel layer, a top source/drain feature, a bottom source/drain feature, a gate structure, and a supporting structure. The channel layer extends in a Z-direction. The top source/drain feature is over and electrically connected to the channel layer. The bottom source/drain feature is under and electrically connected to the channel layer. The gate structure laterally wraps around the channel layer. The supporting structure extends in an X-direction. The supporting structure is in contact with the channel layer, the top source/drain feature, and the bottom source/drain feature in a Y-direction.

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a channel layer extending along a vertical direction, and a top S/D structure formed on the channel layer. The semiconductor structure also includes a bottom S/D structure formed below the channel layer, and a gate structure adjacent to the channel layer. The channel layer is surrounded by the gate structure. The semiconductor structure includes a top inner spacer layer formed on the gate structure, and a top surface of the channel layer is higher than a bottom surface of the top inner spacer layer.

Abstract: A method includes forming a complementary Field-Effect Transistor (CFET) including a first FinFET and a second FinFET. The processes for forming the first FinFET includes forming at least one semiconductor fin having a first total count, and forming a first gate stack on the at least one semiconductor fin. The second FinFET is vertically aligned to the first FinFET. The processes for forming the second FinFET includes forming a plurality of semiconductor fins, wherein the plurality of semiconductor fins have a second total count greater than the first total count, and forming a second gate stack on the plurality of semiconductor fins.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.