Patents by Inventor Jin-Cheng Huang

Jin-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6838900
    Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 4, 2005
    Assignee: VIA Technologies, Inc.
    Inventors: Jin-Cheng Huang, Ching Fu Chuang
  • Patent number: 6744646
    Abstract: A device and method for converting a low voltage signal into a high voltage signal are provided, which can be implemented by using a low voltage CMOS manufacturing process to convert a low voltage signal of 0V to 1.5V into a high voltage signal of 2.5V to 1.25V. According to one preferred embodiment, PMOS transistors are employed to perform voltage level conversion and supply voltages of 1.25V and 2.5V are supplied to the PMOS transistors. During the conversion, no current path exists between the supply voltages thus effectively reducing static power consumption. In addition, the low level of the high voltage signal is outputted through the drain and source of the transistor so that the low level of the high voltage signal can be accurately defined and not affected by manufacturing parameters.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: June 1, 2004
    Assignee: Via Technologies, Inc.
    Inventors: Jin-Cheng Huang, Yen-Mou Huang
  • Patent number: 6590827
    Abstract: A clock circuit for supporting a plurality of memory module types is provided. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The clock circuit includes a clock generator for producing a clock signal and a clock buffer having doubly defined clock pins for outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin is also capable of outputting a second type memory clock signal to the second type memory clock pin. This invention is capable of using just a single clock buffer to drive a plurality of different memory module types.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: July 8, 2003
    Assignee: Via Technologies, Inc.
    Inventors: Nai-Shung Chang, Jin-Cheng Huang
  • Publication number: 20020167331
    Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.
    Type: Application
    Filed: September 28, 2001
    Publication date: November 14, 2002
    Applicant: Via Technologies, Inc
    Inventors: Jin-Cheng Huang, Ching Fu Chuang
  • Publication number: 20020093323
    Abstract: A voltage level rising regulator and method for rising voltage level are implemented by a low voltage CMOS manufacturing process for converting an input voltage of 0V˜1.5V to an output voltage of 2.5V˜1.25V. According to one preferred embodiment of the invention, a 0V voltage is applied to a gate of a PMOS transistor and its source is connected to a voltage of 1.25V. As the PMOS transistor is turned on, its drain is also 1.25V that is further applied to a gate of another PMOS transistor. Then, the source of the PMOS transistor is connected to a voltage of 2.5V. As the PMOS transistor is turned on, the drain of the PMOS transistor can output an output voltage of 2.5V. When a voltage of 1.5V is applied to the regulator, and then is inverted to a voltage of 0V by an inverter. And the 0V voltage is applied to the gate of the PMOS transistor. Its source can be connected to 1.25V.
    Type: Application
    Filed: October 12, 2001
    Publication date: July 18, 2002
    Inventors: Jin-Cheng Huang, Yen-Mou Huang
  • Publication number: 20020060948
    Abstract: A clock circuit for supporting a plurality of memory module types is provided. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The clock circuit includes a clock generator for producing a clock signal and a clock buffer having doubly defined clock pins for outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin is also capable of outputting a second type memory clock signal to the second type memory clock pin. This invention is capable of using just a single clock buffer to drive a plurality of different memory module types.
    Type: Application
    Filed: September 19, 2001
    Publication date: May 23, 2002
    Inventors: Nai-Shung Chang, Jin-Cheng Huang
  • Publication number: 20020000830
    Abstract: A noise-resistant output stage circuit with inverse-feedback control comprising two NMOS transistors. A first NMOS transistor is coupled to a first high voltage via the drain, and coupled to a first input signal via the gate. A second MOS transistor is coupled to a source of the first MOS transistor via the drain, and performing an output terminal of the output stage circuit, therewith the gate of the second MOS transistor receiving a second input signal; an alternative of the first input signal or the second input signal presents a second high voltage and the other presents a grounding, wherein the second high voltage exceeds the first high voltage. Preferably, the second high voltage is greater than twice the first high voltage. In operation, an alternative of the first NMOS transistor or the second NMOS transistor operates within a linear region.
    Type: Application
    Filed: May 22, 2001
    Publication date: January 3, 2002
    Applicant: Via Technologies, Inc.
    Inventor: Jin-Cheng Huang
  • Patent number: 6133757
    Abstract: A high-speed and low-noise output buffer with a slew control function in coordination with a GTL+ signal specification according to the invention. In the output buffer, general and speed driving elements concurrently drives a last output element. As an input signal is changed from a first logic level to a second logic level, the general and speed driving elements simultaneously start functioning. First, the speed driving element pulls down the control voltage of the output element to a potential having a potential difference from an expected final potential. Then, the general driving element pulls down the control voltage to close to the expected final potential. The output potential of the output element changes more quickly at the beginning. When close to the expected final potential, the variation of the output potential slows down.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: October 17, 2000
    Assignee: VIA Technologies, Inc.
    Inventors: Jin-Cheng Huang, Yuantsang Liaw