Abstract: The present invention relates to a method for treating or preventing benign prostatic hyperplasia comprising administering an effective amount of a composition consisting essentially of an Aucklandiae Radix extract as an active ingredient to a subject in need of treating or preventing benign prostatic hyperplasia.

Abstract: The present invention relates to a single nucleotide polymorphism (SNP) for predicting the sensitivity to an anticancer targeted therapeutic formulation, a polynucleotide containing the same, and a method for predicting the sensitivity to an anticancer targeted therapeutic formulation. According to the present invention, it is possible to predict the sensitivity of each individual to a certain anticancer targeted therapeutic formulation, using a small amount of a sample taken from a patient and thus to select a most suitable targeted therapeutic formulation over the entire duration of treatment for the patient.

Abstract: A target advertisement method in a mobile communication terminal includes a first step of, in a web browser, transmitting keywords having high probability indexes among previously stored keywords, to an advertisement server via the Internet in an initially driven state; a second step of, in the advertisement server, selecting advertisements appropriate for the keywords transmitted from the web browser and transmitting the selected advertisements to the web browser via the Internet; a third step of, in the web browser, displaying the advertisements transmitted from the advertisement server on a first screen of the web browser; and a fourth step of implementing an information searching function or a web surfing function in conformity with a user's desire.

Abstract: A web browser system includes a mobile communication terminal configured to implement decoding and parsing for HTML and CSS binary files, execute a JavaScript bytecode, decode an image file, and implement rendering for respective results, for web browsing of a web browser built therein; a proxy server configured to, in correspondence to a web address transmitted thereto, transmit a page access command to a web server of the corresponding web address via a wired network, implement grammar indentifying binary encoding for HTML and CSS transmitted from the web server to decrease capacity, convert quality for an image file to decrease capacity, compile JavaScript into a bytecode to decrease capacity, and transmit those files to the mobile communication terminal via a wireless network; and a web server configured to transmit files constituting a web page including the HTML, CSS, JavaScript and image files, to the proxy server.

Abstract: An advertisement linkage system of a mobile communication terminal, using a proxy server, includes a mobile communication terminal configured to be inputted with a web address from a user on a web browser built therein, transmit the web address to a proxy server via a wireless network, and display web contents and an advertisement received from the proxy server on a display; the proxy server configured to receive the web address from the terminal, transmit a web page access command to a web server via a wide bandwidth wired network, extract keywords from web contents received from the web server, transmit extracted keywords to an advertisement server, and transmit the web contents and an advertisement received from the advertisement server to the terminal; and the advertisement server configured to search an advertisement most appropriate for the keywords received from the proxy server, and transmit the advertisement to the proxy server.

Abstract: A computer system which dynamically extracts multiple threads from a program using a thread binary compiler (TBC), and a simultaneous multithreading (SMT) method. The computer system loads the TBC to a cache and controls the cache such that the TBC divides the program into multiple threads, and the cache loads the program as a recompiled program, whenever the cache loads a program stored in main memory.

Abstract: A multi-level cache system includes a primary cache and a secondary cache that is accessed by a processor later than the primary cache. If the secondary cache is full with data when the processor misses the access to the primary and secondary cache memories, data stored in the secondary cache must be routed to a main memory. In this case, to satisfy the inclusion property of cache, the data migrating to the main memory from the secondary cache is present in the secondary cache, not in the primary cache. The multi-level cache system does not need to access the primary cache to select the data in the secondary cache but not in the primary cache. Thus, it simplifies a logical composition for controlling the miss/replacement, and shortens an operation time therein.

Abstract: A computer system which dynamically extracts multiple threads from a program using a thread binary compiler (TBC), and a simultaneous multithreading (SMT) method. The computer system loads the TBC to a cache and controls the cache such that the TBC divides the program into multiple threads, and the cache loads the program as a recompiled program, whenever the cache loads a program stored in main memory.

Abstract: A cache memory system includes a tag RAM storing tags in a plurality of sets thereof, a data RAM storing data in a plurality of sets corresponding to the tag RAM sets, and a control logic controlling overall functions in the cache memory. The control logic generates set selection signals which designate the sets storing data replaceable with those of the data RAM in accordance with N-bit data representing a replacement condition of data stored in the data RAM sets. The control logic is composed of counters generating the set selection signals synchronous with a predetermined clock signal in order to modify the sets replaceable data in a random order, so that block replacement logic is constructed in a more simplified form though the number of sets increases in a set-associative cache memory.

Abstract: A cache memory system includes a tag RAM storing tags in a plurality of sets thereof, a data RAM storing data in a plurality of sets corresponding to the tag RAM sets, and a control logic controlling overall functions in the cache memory. The control logic generates set selection signals which designate the sets storing data replaceable with those of the data RAM in accordance with N-bit data representing a replacement condition of data stored in the data RAM sets. The control logic is composed of counters generating the set selection signals synchronous with a predetermined clock signal in order to modify the sets replaceable data in a random order, so that block replacement logic is constructed in a more simplified form though the number of sets increases in a set-associative cache memory.

Abstract: A multi-level cache system includes a primary cache and a secondary cache that is accessed by a processor later than the primary cache. If the secondary cache is full with data when the processor misses the access to the primary and secondary cache memories, data stored in the secondary cache must be routed to a main memory. In this case, to satisfy the inclusion property of cache, the data migrating to the main memory from the secondary cache is present in the secondary cache, not in the primary cache. The multi-level cache system does not need to access the primary cache to select the data in the secondary cache but not in the primary cache. Thus, it simplifies a logical composition for controlling the miss/replacement, and shortens an operation time therein.