Abstract: A system includes a first processing component, a second processing component, and an adapted bus linking the first and second processing components. The adapted bus may account for a circuit characteristic or on-chip variation in the system. For example, the bus may be adapted to include a wider data width because of an effect of the on-chip variation that limits performance of the bus at a lower data width. The bus may include a widened data width for a portion of the bus. In that regard, the bus may include a bus expander and a bus narrower for adjusting the data width of the bus.

Abstract: Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

Abstract: Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first block and a second block in a prefetch buffer; associating a first block access with a backward prefetch scheme; associating a second block access with a forward prefetch scheme; and, if the first block is accessed before the second block, then performing a backward prefetch with respect to the first block.

Abstract: Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

Abstract: Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first block and a second block in a prefetch buffer; associating a first block access with a backward prefetch scheme; associating a second block access with a forward prefetch scheme; and, if the first block is accessed before the second block, then performing a backward prefetch with respect to the first block.

Abstract: Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.

Abstract: Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

Abstract: Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first block and a second block in a prefetch buffer; associating a first block access with a backward prefetch scheme; associating a second block access with a forward prefetch scheme; and, if the first block is accessed before the second block, then performing a backward prefetch with respect to the first block.

Abstract: Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.

Abstract: A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.

Abstract: A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.

Abstract: A system and method for identifying which incoming write data is valid and for insuring that stale data does not overwrite valid data within system memory within a symmetrical multiprocessor data processing system. Upon receipt of a Load Miss request from a processor, a stale bit is established and set equal to zero. A determination is then made of which other processor has ownership of the requested cache line. The requested cache line is then transferred in a cache-to-cache transfer from the second processor to the first processor. If the first processor further modifies the cache line and writes back the cache line to system memory before the original owner of the cache line writes back the stale data with an acknowledgment of the cache-to-cache transfer, the stale bit is set to one. Upon receipt from the acknowledgment from the original owner of the cache line, the stale data is dropped when it is determined that the stale bit has been set.