Patents by Inventor Jin-Dah Chen

Jin-Dah Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11830936
    Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Dah Chen, Stan Chen, Han-Wei Wu
  • Publication number: 20230049896
    Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.
    Type: Application
    Filed: April 5, 2022
    Publication date: February 16, 2023
    Inventors: Jin-Dah CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20220262624
    Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.
    Type: Application
    Filed: February 12, 2021
    Publication date: August 18, 2022
    Inventors: Jin-Dah CHEN, Hua-Tai LIN, Han-Wei WU, Jiann-Yuan HUANG
  • Patent number: 11387105
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Publication number: 20220157973
    Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Jin-Dah Chen, Stan Chen, Han-Wei Wu
  • Patent number: 11316033
    Abstract: A method includes forming a work function metal layer over first and second semiconductor fins extending upward from a substrate; forming a sacrificial layer straddling the first semiconductor fin but not overlapping the second semiconductor fin; patterning the first work function metal layer using the sacrificial layer, resulting in a patterned work function metal layer under the sacrificial layer, and a work function metal residue in the vicinity of the second semiconductor fin; selectively forming a protective layer on a side surface of the sacrificial layer and a side surface of the patterned first work function metal layer; removing the work function metal residue after selectively forming the protective layer; after removing the work function metal residue, removing the sacrificial layer and the protective layer; and forming a second work function metal layer over the first and second semiconductor fins.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Stan Chen
  • Patent number: 11239345
    Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Dah Chen, Stan Chen, Han-Wei Wu
  • Publication number: 20210391442
    Abstract: A method includes forming a work function metal layer over first and second semiconductor fins extending upward from a substrate; forming a sacrificial layer straddling the first semiconductor fin but not overlapping the second semiconductor fin; patterning the first work function metal layer using the sacrificial layer, resulting in a patterned work function metal layer under the sacrificial layer, and a work function metal residue in the vicinity of the second semiconductor fin; selectively forming a protective layer on a side surface of the sacrificial layer and a side surface of the patterned first work function metal layer; removing the work function metal residue after selectively forming the protective layer; after removing the work function metal residue, removing the sacrificial layer and the protective layer; and forming a second work function metal layer over the first and second semiconductor fins.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah CHEN, Stan CHEN
  • Publication number: 20200388497
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Patent number: 10755936
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Publication number: 20200251578
    Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Jin-Dah Chen, Stan Chen, Han-Wei Wu
  • Patent number: 10644134
    Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Dah Chen, Stan Chen, Han-Wei Wu
  • Publication number: 20190252193
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Patent number: 10276392
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Publication number: 20180350955
    Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Jin-Dah Chen, Stan Chen, Han-Wei Wu
  • Patent number: 10115796
    Abstract: A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate, forming a material layer in the first, the second and the third trenches, forming a sacrificial layer to fully fill in the remaining first and the second trenches, recessing the sacrificial layer in the first trench and the second trench, recessing the material layer in the first trench and in the second trench. After recessing the material layer, a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the first trench and a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the second trench. The method also includes removing the remaining sacrificial layer in the first trench and the second trench.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Dah Chen, Han-Wei Wu, Ming-Feng Shieh
  • Publication number: 20170309718
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 26, 2017
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Patent number: 9711604
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Publication number: 20170200798
    Abstract: A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate, forming a material layer in the first, the second and the third trenches, forming a sacrificial layer to fully fill in the remaining first and the second trenches, recessing the sacrificial layer in the first trench and the second trench, recessing the material layer in the first trench and in the second trench. After recessing the material layer, a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the first trench and a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the second trench. The method also includes removing the remaining sacrificial layer in the first trench and the second trench.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventors: Jin-Dah Chen, Han-Wei Wu, Ming-Feng Shieh
  • Publication number: 20170194443
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 6, 2017
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen