Abstract: A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: the storage unit comprises a transistor and a capacitor. The transistor comprises a channel, a first electrode, a second electrode, and a gate; the second electrode is connected to a bit line; the first electrode is connected to the capacitor; and the gate surrounds the channel and is connected to the channel by means of a gate insulating layer. The capacitor comprises a first capacitor electrode, a second capacitor electrode and a capacitor dielectric layer; the first capacitor electrode is connected to the first electrode; and the first capacitor electrode, the first electrode, the channel, and the second electrode are of integrated structures, and are formed of a same metal oxide conductive material.

Abstract: A memory includes a three-dimensional storage array located on one side of a substrate, wherein the three-dimensional storage array includes several storage array layers; each storage array layer includes storage units, bit lines perpendicular to the substrate, and word lines parallel to the substrate; each storage array layer further includes a selection circuit, a first select line, a second select line, several third select lines and several low-level potential ends; the first select line and the second select line are parallel to the substrate; the third select lines and the word lines are arranged in one-to-one correspondence; the selection circuit is connected to the word lines, the first select line, the second select line, the several third select lines and the several low-level potential ends; and a plurality of selection circuits are used for determining selected storage array layers, and determining, word lines selected during a read-write operation.

Abstract: Disclosed are a lower casing and a battery pack. The lower casing includes: a base plate; a cold plate, wherein the cold plate is provided with a stamped portion and a peripheral connecting portion, the stamped portion is recessed in a direction away from the base plate, and encloses to form a heat-exchange channel together with the base plate, the peripheral connecting portion surrounds the stamped portion, and the peripheral connecting portion is welded to the base plate; and a first port and a second port, the first port and the second port are both fixedly connected to the base plate, and one of the first port and the second port is in communication with an inlet end of the heat-exchange channel, and the other of the first port and the second port is in communication with an outlet end of the heat-exchange channel.

Abstract: A memory and a manufacturing method therefor, and an electronic device are disclosed. The memory includes transistors, word lines, and bit lines. The word line extends in a direction perpendicular to a substrate. The transistors each include a semiconductor layer located on a sidewall of the word line, and a gate insulating layer arranged between the sidewall of the word line and the semiconductor layer. The bit line includes a bit line main body, and a plurality of first branches corresponding to the plurality of transistors, respectively. The bit line body extends in a first direction parallel to the substrate. The first branches extend towards the semiconductor layer and are connected to the semiconductor layer.

Abstract: The present disclosure provides a memory, an access method therefor and an electronic device.

Abstract: The manufacturing method comprises: Sequentially and alternatively depositing a first insulating layer and a sacrificial layer on a substrate to obtain a stacked structure; etching the stacked structure, forming in the stacked structure a plurality of through holes extending towards the substrate, and depositing a second insulating layer in the through holes; performing patterning etching on the stacked structure provided with the through holes to obtain a patterned sacrificial layer, the patterned sacrificial layer comprising a plurality of bit line regions and a plurality of electrode regions each distributed between any two adjacent bit line regions; and replacing the patterned sacrificial layer with a patterned conduction layer, the patterned conduction layer comprising a plurality of bit lines extending in a first direction and a plurality of electrodes distributed on two sides of the bit lines and connected to the bit lines.

Abstract: A system, vehicle, and method for controlling a vehicle using geo-fence-based activity regulations that change over time. The system includes processor(s) configured to receive a geo-fence identifier that uniquely identifies a geo-fence, obtain one or more activity regulations for the vehicle based on the geo-fence identifier, and control operation of the vehicle according to a set of activity regulations applicable based on a current time. The activity regulations change over time such that a first set of activity regulations applicable at a first time differs from a second set applicable at a second time. At least one of boundaries or restrictions associated with the geo-fence may change over time. The geo-fence may comprise a dynamic indicator that changes over time to reflect changes in the activity regulations. The activity regulations may change periodically, in accordance with a pre-set schedule, or in response to a detected event or condition.

Abstract: The present disclosure relates to the technical field of semiconductors. The present disclosure relates to a memory, a manufacturing method therefor and an electronic device, and is used for improving the performance of the memory.

Abstract: A 3D stacked semiconductor device and a manufacturing method therefor, a 3D memory, and an electronic device. The 3D stacked semiconductor device includes a plurality of transistors and a word line (40). The plurality of transistors are distributed on different layers, stacked in a direction perpendicular to a substrate (20) and distributed periodically. A transistor includes a gate electrode (26), a semiconductor layer (23) surrounding the side wall of the gate electrode (26), and a gate insulating layer (24) arranged between the side wall of the gate electrode (26) and the semiconductor layer (23). The gate electrode (26) extends in the direction perpendicular to the substrate (20). The gate electrode (26) of each transistor is a part of the word line (40); and the plurality of semiconductor layers (23) of the plurality of transistors are arranged at intervals and disconnected.

Abstract: A CXL memory module, a memory processing method, and a computer system. A controller chip is configured to execute the following operations: establishing a logical-physical address translation table; receiving an operation instruction based on a logical address, translating the logical address into a physical address of a DRAM chip on the basis of the logical-physical address translation table, and performing operation according to the physical address; receiving a memory application instruction through a CXL interface, the memory application instruction carrying size information of a memory; and performing memory allocation according to the size information of the memory, and returning a memory address allocated for a main body to the main body.

Abstract: A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, which are distributed in different layers and are stacked in a direction perpendicular to a substrate. Each transistor comprises: a first electrode; a second electrode; an insulation portion, which connects the first electrode and the second electrode; a semiconductor layer, by which the first electrode, the insulation portion and the second electrode are surrounded; a gate electrode, by which a side wall of the semiconductor layer is surrounded; and a gate insulation layer, which is disposed between the gate electrode and the semiconductor layer, wherein the first electrode, the insulation portion and the second electrode are connected to form an integrated structure.

Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

Abstract: A semiconductor device, a manufacturing method therefor, and an electronic apparatus are disclosed. The semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; a word line, penetrating the different layers and extending in the direction perpendicular to the substrate; the transistor includes a first electrode, a gate insulating layer, a semiconductor layer surrounding side walls of the word line, and a protective layer disposed between the semiconductor layer and side walls of the gate insulating layer; the first electrode is provided in a first groove of the semiconductor layer.

Abstract: Provided are a transistor, a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device. The transistor includes a first electrode and a second electrode arranged on a substrate, a semiconductor layer arranged between the first electrode and the second electrode, and a gate electrode insulated from the semiconductor layer; the first electrode and the second electrode are separated in a first direction parallel to the substrate; the gate electrode extends along a second direction parallel to the substrate, the gate electrode includes a sidewall extending along the second direction and two end surfaces, one end surface is configured to be connected with a word line; at least a portion of the sidewall of the gate electrode is surrounded by a semiconductor layer; the first direction intersects with the second direction.

Abstract: A system for controlling a vehicle, including one or more communication modules and one or more processors operably coupled to the communication modules. The one or more processors are configured to individually or collectively: receive a geo-fence identifier associated with geo-fence information, where the geo-fence identifier uniquely identifies the geo-fence from other geo-fences; obtain one or more activity regulations for the vehicle based on the geo-fence identifier; and control operation of the vehicle according to the one or more activity regulations.

Abstract: A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor, the first transistor comprises a first electrode, a second electrode, and two independent gates, i.e., a first gate and a second gate; the second transistor comprises a first electrode, a second electrode, and a gate; the first gate of the first transistor is used as a first word line connecting end; the gate of the second transistor is used as a second word line connecting end; and the second gate of the first transistor is connected to the first electrode of the second transistor.

Abstract: A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

Abstract: A neural network model training method includes: constructing a first neural network architecture, where the first neural network architecture includes M basic unit layers, each of the M basic unit layers includes a plurality of basic units, and the plurality of basic units includes at least a first-type basic unit and a second-type basic unit; and obtaining a target model through training based on datasets respectively corresponding to a plurality of tasks and the first neural network architecture, where the target model includes a plurality of task paths, at least some of the plurality of task paths include N basic units selected from some of the M basic unit layers, and N<M.

Abstract: A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.