Abstract: A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.

Abstract: Compositions including a thermosetting polymer network and a mechanophore covalently bonded to the thermosetting polymer network are provided. Substrates including the compositions are provided. In addition, methods of making the compositions and methods of monitoring stress on a substrate comprising the compositions are provided.

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

Abstract: A multi-target kinase inhibitor is shown in formula (I), in which R is selected from formula (a), formula (b), formula (c), formula (d), formula (e) and formula (f). The multi-target kinase inhibitor can effectively inhibit the enzymatic activities of RET, VEGFR3 and PDGFRA, and can effectively treat diseases that are regulated and controlled by multi-target kinases and are related to abnormal signal transduction pathways of the multi-target kinases, including cancers of breast, respiratory tract, brain, reproductive organ, digestive tract, urinary tract, eye, liver, skin, head and/or neck and distant metastatic cancers thereof, and lymphoma, sarcoma, leukemia and the like. The active ingredients of the pharmaceutical composition of the present invention comprise a multi-target kinase inhibitor, which accounts for 1-50 wt % of the composition.

Abstract: An aerial vehicle includes a communication unit configured to receive a wireless signal from a geo-fencing device, and a flight controller configured to generate one or more control signals that cause the aerial vehicle to operate in accordance with a set of flight regulations generated based on the wireless signal. The geo-fencing device is configured not for landing of the aerial vehicle. The set of flight regulations includes rules for controlling at least one of the aerial vehicle, a carrier carried by the aerial vehicle, or a payload of the aerial vehicle.

Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Abstract: An unmanned aerial vehicle (UAV) includes a sensor configured to detect an indicator of a geo-fencing device; and a flight controller configured to generate one or more signals that cause the UAV to operate in accordance with a set of flight regulations that are generated based on the detected indicator of the geo-fencing device.

Abstract: A system for controlling a vehicle, including one or more communication modules and one or more processors operably coupled to the communication modules. The one or more processors are configured to individually or collectively: receive a geo-fence identifier associated with geo-fence information, where the geo-fence identifier uniquely identifies the geo-fence from other geo-fences; obtain one or more activity regulations for the vehicle based on the geo-fence identifier; and control operation of the vehicle according to the one or more activity regulations.

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

Abstract: A method for regulating an unmanned aerial vehicle (UAV) includes receiving a UAV identifier and one or more types of contextual information broadcasted by the UAV. The UAV identifier uniquely identifies the UAV from other UAVs. The one or more types of contextual information includes at least geographical information of the UAV. The method further includes authenticating, via an authentication device, an identity of the UAV based on the UAV identifier to determine whether the UAV is authorized for operation, and transmitting a signal to a remote device in response to determining whether the UAV is authorized for operation.

Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.

Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.

Abstract: A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.

Abstract: An object computational storage system, a data processing method, a client end and a storage medium are disclosed, belonging to the field of electrical digital data processing, including a storage control device and a storage chip or a storage disk connected thereto. The storage control device is a computational storage management system, and performs the following processing: receiving an external data processing request, parsing information of a specified storage object, information of a specified function, and information of input data carried by the data processing request; when it is determined that calling the specified function for the specified storage object is supported, calling the specified function to perform computation on data of the specified storage object according to the input data; and returning a computation result to a sender of the data processing request.

Abstract: A resonant amplitude grating mark has a periodic structure configured to scatter radiation incident on the mark. The scattering is mainly by coupling of the incident radiation to a waveguiding mode in the periodic structure. The effective refractive indexes and lengths of portions of the periodic structure are configured to provide an optical path length of the unit cell in the direction of periodicity that essentially equals an integer multiple of a wavelength present in the radiation. The effective refractive indexes and lengths of the portions are also configured to provide an optical path length of the second portion in the direction of periodicity that is selected from 0.30 to 0.49 of the wavelength present in the spectrum of the radiation.

Abstract: Disclosed is a process of manufacturing a thickened angle ring. The process includes the steps of: soaking wet paper into deionized water for 1 hour; beating bonding surfaces of the two pieces of wet paper into fuzzed and rough surfaces; placing a heat resisting polyester film and a nylon net on a mold, and placing one fuzzed wet paper on the mold in contact with the nylon net on smooth side thereof; placing the other wet paper in contact with the fuzzed surface of the previous wet paper on fuzzed side thereof, and beating until the wet paper fits the mold; placing a further heat resisting polyester film and a further nylon net on the two pieces of wet paper for pressing.