Patents by Inventor Jin do Byun
Jin do Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230360689Abstract: A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.Type: ApplicationFiled: April 26, 2023Publication date: November 9, 2023Inventors: Jun Young Park, Joo Hwan Kim, Jin Do Byun, Eun Seok Shin, Hyun Sub Rie, Hyun-Yoon Cho, Jung Hwan Choi
-
Publication number: 20230143365Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.Type: ApplicationFiled: June 29, 2022Publication date: May 11, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Joo Hwan KIM, Jun Young PARK, Jin Do BYUN, Kwang Seob SHIN, Eun Seok SHIN, Hyun-Yoon CHO, Young Don CHOI, Jung Hwan CHOI
-
Publication number: 20230138845Abstract: A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.Type: ApplicationFiled: July 6, 2022Publication date: May 4, 2023Inventors: Joo Hwan KIM, Su Cheol LEE, Jin Do BYUN, Eun Seok SHIN, Young Don CHOI, Jung Hwan CHOI
-
Publication number: 20220157845Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.Type: ApplicationFiled: July 26, 2021Publication date: May 19, 2022Inventors: MIN JAE LEE, Jin Do Byun, Young-Hoon Son, Young Don Choi, Pan Suk Kwak, Myung Hun Lee, Jung Hwan Choi
-
Patent number: 11244738Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.Type: GrantFiled: August 4, 2020Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae Hoon Na, Jang Woo Lee, Jin Do Byun, Jeong Don Ihm
-
Patent number: 11017877Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.Type: GrantFiled: August 12, 2019Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae Hoon Na, Jang Woo Lee, Jin Do Byun, Jeong Don Ihm
-
Publication number: 20200365225Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Hoon NA, Jang Woo LEE, Jin Do BYUN, Jeong Don IHM
-
Publication number: 20200227131Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.Type: ApplicationFiled: August 12, 2019Publication date: July 16, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Hoon NA, Jang Woo LEE, Jin Do BYUN, Jeong Don IHM
-
Patent number: 9543628Abstract: A folded corrugated substrate integrated waveguide is disclosed.Type: GrantFiled: November 29, 2013Date of Patent: January 10, 2017Assignee: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Hai Young Lee, Dae Keun Cho, Jin do Byun
-
Patent number: 9525211Abstract: An antenna and a communication system with the antenna are provided. The antenna may include a first layer including a plurality of folded stubs, a second layer including a pattern of the folded stubs, and a third layer connected to ground is disposed between the first layer and the second layer.Type: GrantFiled: January 2, 2014Date of Patent: December 20, 2016Assignees: Samsung Electronics Co., Ltd., Ajou University Industry-Academic Cooperation FoundationInventors: Byung Moo Lee, Byung Chang Kang, Jong Ho Bang, Jin Do Byun, Hai-Young Lee
-
Publication number: 20150318598Abstract: A folded corrugated substrate integrated waveguide is disclosed.Type: ApplicationFiled: November 29, 2013Publication date: November 5, 2015Inventors: Hai Young LEE, Dae Keun CHO, Jin do BYUN
-
Patent number: 9136579Abstract: Provided is a phase shifter using a substrate integrated waveguide (SIW). The phase shifter includes: a substrate; and a waveguide integrated on the substrate, wherein the waveguide includes an input port, an out port, two columns of via walls which are separated by a width of the waveguide and are arranged parallel to each other, and either a plurality of air holes which are formed to shift a phase of a signal between the input port and the output port or a plurality of rods, each including an air hole and a dielectric material inserted into the air hole.Type: GrantFiled: November 4, 2010Date of Patent: September 15, 2015Assignee: AJOU UNIVERSITY INDUSTRY COOPERATION FOUNDATIONInventors: Hai-Young Lee, Ki-Bum Kang, Jin do Byun
-
Publication number: 20140184456Abstract: An antenna and a communication system with the antenna are provided. The antenna may include a first layer including a plurality of folded stubs, a second layer including a pattern of the folded stubs, and a third layer connected to ground is disposed between the first layer and the second layer.Type: ApplicationFiled: January 2, 2014Publication date: July 3, 2014Applicants: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung Moo LEE, Byung Chang KANG, Jong Ho BANG, Jin Do BYUN, Hai-Young LEE
-
Publication number: 20120274419Abstract: Provided is a phase shifter using a substrate integrated waveguide (SIW). The phase shifter includes: a substrate; and a waveguide integrated on the substrate, wherein the waveguide includes an input port, an out port, two columns of via walls which are separated by a width of the waveguide and are arranged parallel to each other, and either a plurality of air holes which are formed to shift a phase of a signal between the input port and the output port or a plurality of rods, each including an air hole and a dielectric material inserted into the air hole.Type: ApplicationFiled: November 4, 2010Publication date: November 1, 2012Inventors: Hai-Young Lee, Ki-Bum Kang, Jin do Byun