Patents by Inventor Jin do Byun

Jin do Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157845
    Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: May 19, 2022
    Inventors: MIN JAE LEE, Jin Do Byun, Young-Hoon Son, Young Don Choi, Pan Suk Kwak, Myung Hun Lee, Jung Hwan Choi
  • Patent number: 11244738
    Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Hoon Na, Jang Woo Lee, Jin Do Byun, Jeong Don Ihm
  • Patent number: 11017877
    Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Hoon Na, Jang Woo Lee, Jin Do Byun, Jeong Don Ihm
  • Publication number: 20200365225
    Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae Hoon NA, Jang Woo LEE, Jin Do BYUN, Jeong Don IHM
  • Publication number: 20200227131
    Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.
    Type: Application
    Filed: August 12, 2019
    Publication date: July 16, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae Hoon NA, Jang Woo LEE, Jin Do BYUN, Jeong Don IHM
  • Patent number: 9543628
    Abstract: A folded corrugated substrate integrated waveguide is disclosed.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: January 10, 2017
    Assignee: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Hai Young Lee, Dae Keun Cho, Jin do Byun
  • Patent number: 9525211
    Abstract: An antenna and a communication system with the antenna are provided. The antenna may include a first layer including a plurality of folded stubs, a second layer including a pattern of the folded stubs, and a third layer connected to ground is disposed between the first layer and the second layer.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: December 20, 2016
    Assignees: Samsung Electronics Co., Ltd., Ajou University Industry-Academic Cooperation Foundation
    Inventors: Byung Moo Lee, Byung Chang Kang, Jong Ho Bang, Jin Do Byun, Hai-Young Lee
  • Publication number: 20150318598
    Abstract: A folded corrugated substrate integrated waveguide is disclosed.
    Type: Application
    Filed: November 29, 2013
    Publication date: November 5, 2015
    Inventors: Hai Young LEE, Dae Keun CHO, Jin do BYUN
  • Patent number: 9136579
    Abstract: Provided is a phase shifter using a substrate integrated waveguide (SIW). The phase shifter includes: a substrate; and a waveguide integrated on the substrate, wherein the waveguide includes an input port, an out port, two columns of via walls which are separated by a width of the waveguide and are arranged parallel to each other, and either a plurality of air holes which are formed to shift a phase of a signal between the input port and the output port or a plurality of rods, each including an air hole and a dielectric material inserted into the air hole.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 15, 2015
    Assignee: AJOU UNIVERSITY INDUSTRY COOPERATION FOUNDATION
    Inventors: Hai-Young Lee, Ki-Bum Kang, Jin do Byun
  • Publication number: 20140184456
    Abstract: An antenna and a communication system with the antenna are provided. The antenna may include a first layer including a plurality of folded stubs, a second layer including a pattern of the folded stubs, and a third layer connected to ground is disposed between the first layer and the second layer.
    Type: Application
    Filed: January 2, 2014
    Publication date: July 3, 2014
    Applicants: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Moo LEE, Byung Chang KANG, Jong Ho BANG, Jin Do BYUN, Hai-Young LEE
  • Publication number: 20120274419
    Abstract: Provided is a phase shifter using a substrate integrated waveguide (SIW). The phase shifter includes: a substrate; and a waveguide integrated on the substrate, wherein the waveguide includes an input port, an out port, two columns of via walls which are separated by a width of the waveguide and are arranged parallel to each other, and either a plurality of air holes which are formed to shift a phase of a signal between the input port and the output port or a plurality of rods, each including an air hole and a dielectric material inserted into the air hole.
    Type: Application
    Filed: November 4, 2010
    Publication date: November 1, 2012
    Inventors: Hai-Young Lee, Ki-Bum Kang, Jin do Byun