Abstract: Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.

Abstract: Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A panel and its drive method are provided. The panel includes: a substrate, an array layer and an electrode array layer, where the array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer; the substrate includes a plurality of drive units arranged in an array, a plurality of scan line groups and a plurality of data line groups; the scan line group includes first scan lines and second scan lines adjacent to the first scan lines, extending in a first direction; and the data line group includes first data lines and second data lines adjacent to the first data lines, extending in a second direction.

Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal. The step-up unit includes a first module, a second module and a first capacitor. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor at a first time period which generates a voltage difference between two electrodes of the first capacitor, and to transmit the signal of the fourth signal input terminal to the second electrode of the first capacitor at a second time period which further increases a signal of the first electrode of the first capacitor.

Abstract: A driving circuit includes a first signal-input terminal, a second signal-input terminal, a third signal-input terminal, a fourth signal-input terminal, a signal-output terminal, and a voltage-boosting unit including a first module, a second module, a third module, and a first capacitor. The first module transmits the signal at the third signal-input terminal to a first terminal of the first capacitor during a first time period, and blocks signal transmission during a second time period. During the first time period and the second time period, the second module transmits the signal at the third signal-input terminal to the third module to allow the signal at the fourth signal-input terminal to be transmitted to a second terminal of the first capacitor. During a third time period, the second module and the third module both block signal transmission. The first terminal of the first capacitor is connected to the signal-output terminal for output.

Abstract: Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.

Abstract: A light-emitting module includes a light-emitting panel which includes a first rigid substrate, a flexible substrate, a circuit layer, a light-emitting element, and a driver chip. The flexible substrate includes a light-emitting region, a bending region, and an epitaxial region, and the light-emitting region and the epitaxial region are located on two ends of the bending region. The circuit layer includes a first connection terminal located on the epitaxial region and the driver chip is bonded to the first connection terminal. The light-emitting element is located on the light-emitting region, and the light-emitting element emits light toward the first rigid substrate. The flexible substrate is bent in the bending region and the flexible substrate in the epitaxial region is bent to a side of the light-emitting elements facing away from the first rigid substrate. The process difficulty can be reduced and the product yield can be improved.

Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.

Abstract: In an array substrate, an electronic paper display panel and a drive method thereof, and a display device, a display area includes multiple sub-display areas. A plurality of scanning lines in each sub-display area are electrically insulated from each other, corresponding scanning lines in different sub-display areas are electrically connected to each other and display time of each sub-display area is controlled through control signal lines. When a control chip and a flexible circuit board are employed, only a small number of control chips and/or flexible circuit boards, or even only one control chip and/or one flexible circuit board, may drive multiple sub-display areas to display pictures.

Abstract: Provided are an array substrate, an electronic paper display panel and a drive method thereof and a display device. A display area includes a plurality of sub-display areas, a plurality of data lines in each sub-display area are electrically insulated from each other, corresponding data lines in different sub-display areas are electrically connected to each other, and a control signal line is configured to control display time of each sub-display area. When a control chip and a flexible circuit board are employed, only a small number of control chips and flexible circuit boards may drive the plurality of sub-display areas to display pictures.

Abstract: Chip package method and chip package structure are provided. The chip package method includes: providing a transparent substrate including a first side and a second side; coating the first side of the transparent substrate with an organic polymer material layer; depositing a protective layer on the organic polymer material layer; forming alignment parts on the protective layer; attaching a plurality of chips including metal pins; forming an encapsulating layer on the protective layer; polishing the encapsulating layer to expose the metal pins; forming a first insulating layer; forming first through holes in the first insulating layer; forming metal parts extending along sidewalls of the first through holes; and irradiating the second side of the transparent substrate by a laser to lift off the transparent substrate. The metal parts are insulated from each other and electrically connected to the metal pins.

Abstract: Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A microfluidic chip, a method for driving a microfluidic chip and an analysis apparatus are provided. An exemplary microfluidic chip includes a substrate; a number of M driving electrodes disposed on a side of the substrate and arranged along a first direction; and a number of N signal terminals electrically connected to the number of M driving electrodes. Any three adjacent driving electrodes are connected to different signal terminals, respectively; a number of A of the number of M driving electrodes are connected to a same signal terminal; and M, N and A are positive integers, and M?4, N?3, M>N, and A?2.

Abstract: A display component and a display device are provided. The display component includes a display panel including a first substrate, a thin-film transistor array layer, a second substrate and a coil-containing film layer. The coil-containing film layer at least includes a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer. The first metal layer includes at least one first coil and the second metal layer includes at least one signal line, where the one first coil of the first metal layer is electrically connected to one or two signal lines of the second metal layer. An orthographic projection of the first coil on the first substrate is at least partially in the display region. The display component further includes a coil drive circuit, where the coil drive circuit is electrically connected to each of the first coil and the signal line, respectively.

Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A 3D printed display panel includes two opposing substrates and a black matrix formed on one of the substrates. The light proof areas of the black matrix include multiple first portions, multiple second portions and multiple third portions arranged to form a grid structure. The first portions and the third portions are alternately arranged in a direction of the scanning lines, the second portions and the third portions are alternately arranged in a direction of the data lines. Meshes of the grid structure are aperture zones of the black matrix. The aperture zones are in one-to-one correspondence with the pixel units. A vertical projections of the scanning lines and the data lines on the second substrate are located in the lightproof areas; where a minimum width of one first portion is X, a minimum width of one second portion is Y, and |X?Y|?2 ?m.

Abstract: An array substrate and a display panel are provided. The array substrate includes a base layer, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a first electrode layer, and a reflective layer successively stacked along a direction perpendicular to a plane in which the base layer is located. The second metal layer is used to form a source and a drain of a thin film transistor. The first electrode layer is used to form a pixel electrode. The second insulating layer is provided with a through-hole. The pixel electrode is connected to the drain of the thin film transistor through the through-hole. The reflective layer is provided with a first through-hole, and an orthographic projection of the first through-hole onto the base layer covers an orthographic projection of the through-hole onto the base layer.

Abstract: A display component and a display device are provided. The display component includes a display panel including a first substrate, a thin-film transistor array layer, a second substrate and a coil-containing film layer. The coil-containing film layer at least includes a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer. The first metal layer includes at least one first coil and the second metal layer includes at least one signal line, where the one first coil of the first metal layer is electrically connected to one or two signal lines of the second metal layer. An orthographic projection of the first coil on the first substrate is at least partially in the display region. The display component further includes a coil drive circuit, where the coil drive circuit is electrically connected to each of the first coil and the signal line, respectively.

Abstract: A touch-control display panel, driving method, and a touch-control display device are provided. The touch-control display panel includes: a display area including a plurality of pixels; a non-display area; a first substrate; and a second substrate opposing the first substrate. A portion of the first substrate in the first region includes a pixel electrode layer and a first electrode layer. The first electrode layer is located on a side of the pixel electrode layer away from the second substrate and includes a plurality of first electrodes. The pixel electrode layer includes a plurality of pixel electrodes. A touch-control electrode layer is located on a side of the second substrate toward the first substrate and includes a plurality of touch-control electrodes. Along a direction perpendicular to the touch-control display panel, each touch-control electrode of the plurality of the touch-control electrode overlaps with and connects with one or more first electrode of the plurality of the first electrodes.

Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.