Patents by Inventor Jin Gu

Jin Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140182915
    Abstract: The present invention relates to a circuit board. A circuit board in accordance with an embodiment of the present invention includes a base substrate; an interlayer insulating layer covering the base substrate; a via structure passing through at least the interlayer insulating layer of the base substrate and the interlayer insulating layer in the vertical direction; and an etch stop pattern disposed on the interlayer insulating layer in the horizontal direction to surround the via structure and made of an insulating material.
    Type: Application
    Filed: October 22, 2013
    Publication date: July 3, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung HAN, Young Do KWEON, Jin Gu KIM, Hyung Jin JEON, Yoon Su KIM
  • Publication number: 20140174809
    Abstract: Disclosed herein is a circuit board including: a core layer including a via hole; a metal film covering an inner wall of the via hole; a circuit pattern connected to the metal film on the core layer; and a plug surrounded by the metal film in the via hole and having a thickness thinner than a thickness of the core layer.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 26, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook PARK, Jae Kul Lee, Jin Gu Kim, Chang Bae Lee
  • Publication number: 20140176278
    Abstract: There is provided an inductor, including a circuit board having an input and output terminal formed on a lower surface thereof, a connection pad formed on an upper surface thereof, and a via electrically connecting the input and output terminal and the connection pad, a coil having both ends joined to the connection pad and wound in a circular or a polygonal spiral shape in a longitudinal direction of the circuit board so as to have one or more turns, and a body stacked on the circuit board such that the coil and the connection pad are embedded therein.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Hwan LEE, Seung Wook PARK, Christian ROMERO, Young Do KWEON, Jin Gu KIM
  • Publication number: 20140166347
    Abstract: Disclosed herein is a printed circuit board, including: a base substrate; and a circuit pattern formed on the base substrate, including a conductive filler therein, and having roughness formed on a surface thereof.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 19, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yoon Su Kim, Sung Han, Jin Gu Kim, Young Do Kweon
  • Publication number: 20140124258
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a core layer having a first circuit wiring layer formed on one surface or both surfaces thereof; an insulating layer laminated, as at least one layer, on one surface or both surfaces of the core layer; and a second circuit wiring layer formed on one surface of the insulating layer, wherein a conductive core is included in upper and lower insulating layers contacting the second circuit wiring layer requiring an electromagnetic wave shielding, or the conductive core is included in the insulating layer or the core layer contacting the first circuit wiring layer requiring the electromagnetic wave shielding.
    Type: Application
    Filed: March 14, 2013
    Publication date: May 8, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Wook PARK, Dong Hwan Lee, Jin Gu Kim, Chang Bae Lee, Christian Romero
  • Patent number: 8704350
    Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: April 22, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Jing Li Yuan, Jong Yun Lee
  • Publication number: 20140104798
    Abstract: Disclosed herein are a hybrid lamination substrate and a manufacturing method thereof. The hybrid lamination substrate includes: a core layer; at least one first insulating layer that is made of a photosensitive resin material and is formed on an upper portion, a lower portion, or upper and lower portions of the core layer; and at least one second insulating layer that is made of a non-photosensitive resin material and is formed on the upper portion, the lower portion, or the upper and lower portions of the core layer. Further, a package substrate including the same and a manufacturing method of a hybrid lamination substrate are proposed.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 17, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Dong Hwan LEE, Romero CHRISTIAN, Young Do KWEON, Jin Gu KIM
  • Patent number: 8685852
    Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Gu Kim
  • Publication number: 20140077896
    Abstract: The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 20, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Hwan LEE, Seung Wook Park, Christian Romero, Young Do Kweon, Jin Gu Kim
  • Publication number: 20140063968
    Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK hynix Inc.
    Inventors: Jung Woon Shim, Sung Jae Chung, Jin Gu Kim, Dong Hwan Lee, Seung Won Kim, Su Min Yi
  • Publication number: 20140056472
    Abstract: Various arrangements for identifying a location of a hand of a person are presented. A group of pixels may be identified in an image of a scene as including the person. A reference point may be set for the group of pixels identified as the person. The hand may be identified as using a local distance maximum from the reference point. An indication, such as coordinates, of the location of the hand may be output based on the local distance.
    Type: Application
    Filed: February 26, 2013
    Publication date: February 27, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventor: Jin Gu
  • Publication number: 20140056471
    Abstract: Various arrangements for modeling a scene are presented. A plurality of images of the scene captured over a period of time may be received, each image comprising a plurality of pixels. A plurality of background models may be created using the plurality of images. At least one background model may be created for each pixel of the plurality of pixels. A plurality of foreground models may be created using the plurality of images. A foreground model may be created for each pixel of at least a first subset of pixels of the plurality of pixels. The background models and the foreground models may be indicative of the scene over the period of time.
    Type: Application
    Filed: February 26, 2013
    Publication date: February 27, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventor: Jin Gu
  • Patent number: 8658467
    Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Yuan Jing Li, Jong Yun Lee
  • Patent number: 8644635
    Abstract: An image processing method and an image processing apparatus, the method including: generating a blurry image by using a maximum telephoto image among N (where N is a natural number equal to or greater than 2) live view images; generating an alpha map by using two or more images of the N live view images; and generating a soft focus image by combining the maximum telephoto image and the blurry image by using the alpha map.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-chul Han, Emi Arai, Yang-lim Choi, Jin-gu Jeong, Sang-jin Lee
  • Patent number: 8624128
    Abstract: A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ju-Pyo Hong, Young-Do Kweon, Jin-Gu Kim, Seon-Hee Moon, Dong-Jin Lee, Seung-Wook Park
  • Publication number: 20130312254
    Abstract: The present invention relates to a method for manufacturing a valuable-metal sulfuric-acid solution from a waste battery, and to a method for manufacturing a positive electrode active material. The method for manufacturing the valuable-metal sulfuric-acid solution includes: a step of obtaining valuable-metal powder containing lithium, nickel, cobalt, and manganese from waste batteries; a step of acid-leaching the valuable-metal powder under a reducing atmosphere in order to obtain a leaching solution; and a step of separating the lithium from the leaching solution so as to obtain a sulfuric-acid solution containing the nickel, cobalt, and manganese.
    Type: Application
    Filed: August 18, 2011
    Publication date: November 28, 2013
    Applicant: KOREA INSTITUTE OF GEOSCIENCE AND MINERAL RESOURCES
    Inventors: Soo Kyung Kim, Jin Gu Kang, Dong Hyo Yang, Jeong Soo Sohn, Shun Myung Shin
  • Patent number: 8583041
    Abstract: An operating method for a user interface in a portable terminal and an apparatus thereof are provided. The operating method for a user interface in a portable terminal includes registering Bluetooth connection information in a phone book of the portable terminal, and displaying peripheral Bluetooth device information and phone book information on a screen indicating a searching result for peripheral Bluetooth devices. The method allows a user to easily and rapidly perform Bluetooth communication connection with another user trying performing Bluetooth communication upon using a Bluetooth communication function of the portable terminal.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin Gu Lee
  • Patent number: 8507393
    Abstract: Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO2, 15-20 mol % of B2O3, 0.1-5 mol % of one or more alkali metal oxide selected from Li2O and Na2O, and 0.1-30 mol % of one or more alkaline earth metal oxide selected from MgO, CaO, SrO and ZnO; and 30-60 wt % of a ceramic filler represented by Chemical Formula 1: (Zn1-xMgx)2SiO4??(1) wherein 0?x?1. The disclosed low temperature co-fired ceramic (LTCC) composition is sinterable at low temperature, with a relative density of at least 95% in the temperature range of 800-900° C., is capable of minimizing electric loss, with a dielectric constant of 4-7 and a very low dielectric loss, and is applicable from the low-frequency band to the millimeter-wave band of 60 GHz or more.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: August 13, 2013
    Assignee: Korea Institute of Science and Technology
    Inventors: Jeong Hyun Park, Jin Gu Kang, Young Jin Choi, Jae Gwan Park
  • Patent number: 8502295
    Abstract: A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: August 6, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jin Gu Kim
  • Publication number: 20130169382
    Abstract: Disclosed herein are a common mode filter and a method for manufacturing the same. The common mode filter includes a first insulator sheet; a first circuit layer having a first-layered first coil and a first-layered second coil alternately and separately arranged; a second insulator sheet laminated on the first circuit layer; and a second circuit layer having a second-layered first coil and a second-layered second coil alternately and separately arranged, the second-layered first coil being connected to the first-layered first coil and the second-layered second coil being connected to the first-layered second coil through the plurality of penetration holes.
    Type: Application
    Filed: May 15, 2012
    Publication date: July 4, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Gu Kim, Jong Yun Lee, Young Do Kweon, Chang Bae Lee, Young Seuck Yoo