Abstract: The invention provides a novel scheme to match the clock rates along a single transmission channel. The rate matching aspect of this invention receives a character stream synchronized by a first clock and buffers the character streams. Buffered characters are then transmitted over an output channel synchronized by a second clock. The rate matching system removes one or more filler or removable characters from the output channel if an overflow condition is detected and inserts one or more filler or removable characters in the output channel if an underflow condition is detected.

Abstract: The invention provides a novel scheme to align data streams across multiple transmission channels and match multiple transmissions with one receiving rate. The channel aligning aspect of this invention detects the occurrence of an aligning character in a plurality of input channel character streams, buffers the character stream until an aligning character has been detected on every input channel. The channel aligning system transmits filler characters over every output channel corresponding to an input channel where an aligning character has been received if an aligning character has not been detected on every input channel. The aligning system then synchronously transmits the buffered characters, starting with the aligning character and proceeding with the subsequently received characters. The rate matching aspect of this invention receives a plurality of character streams synchronized by a first clock and buffers the character streams.

Abstract: Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in, first-out sub-buffer. Each data transfer channel communicates transfer requests to the arbiter when data is present in the FIFO. When data transfer to or from the FIFO nears an overrun or underrun condition, the data channel issues an urgent request to the arbiter state machine. The arbiter state machine prioritizes data transfer requests for enabling transfer between the buffer memory and data channels. Once a data transfer is in process it continues uninterrupted unless an urgent request is received from another device. In addition, the invention includes a refresh circuit for the dynamic RAM incorporating similar request and urgent request signals provided to the arbiter state machine for resolution.

Abstract: The present invention provides an architecture for sampling incoming asynchronous data pulses and providing synchronous output pulses having a constant pulse width. The invention has an input stage comprising a toggling flip-flop receiving the asynchronous pulses on the clock input. The complementary output of the flip-flop is provided to a dual path synchronizer stage followed by a dual path one-shot stage to terminate the synchronized pulse.