Abstract: A method of manufacturing a flash memory device and a flash memory device in which a tunnel oxide layer and a first polysilicon pattern are formed on and/or over a semiconductor substrate. A second polysilicon pattern and a third polysilicon pattern are formed on and/or over a sidewall of the first polysilicon pattern and a dielectric layer and a polysilicon layer formed on and/or over the first, second and third polysilicon patterns. An etching process is performed to form a tunnel oxide layer pattern, a dielectric pattern, and a fourth polysilicon pattern.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing the same that may include a tunnel oxide layer on and/or over a semiconductor substrate having source and drain regions. The tunnel oxide layer may have a first width The flash memory device may include a first polysilicon pattern and a second polysilicon pattern on and/or over the tunnel oxide layer and a dielectric pattern on and/or over the tunnel oxide layer, where the first and second polysilicon patterns may be provided. It may also include a third polysilicon pattern on and/or over the dielectric pattern, the third polysilicon pattern having a second width, and a spacer formed on and/or over sidewalls of the first, second and third polysilicon patterns, the dielectric pattern and the tunnel oxide pattern. According to embodiments, the second width may be greater than the first width.

Abstract: A method includes forming trenches in a semiconductor substrate by etching the semiconductor substrate; and then forming a first ion injection layer in sidewalls of the trenches at an active region of the semiconductor substrate; and then forming a second ion injection layer in a substantially horizontally extending surface of the active region located between the trenches; and then performing a threshold voltage adjusting implant on at least the active region, wherein the first ion injection layer and the second ion injection layer overlap at a portion of the active region to provide the overlapping portion with a higher doping concentration than a non-overlapping portion of the active region; and then forming a gate structure on the active region.

Abstract: A method of fabricating a semiconductor device includes forming first spacers formed of a TEOS layer and second spacers formed of a first nitride layer on sidewalls of a gate electrode formed on a semiconductor substrate, and then forming source/drain regions in the semiconductor substrate using the first and second spacers and the gate electrode as masks, and then removing the second spacers, and then depositing a second nitride layer on an entire surface of the semiconductor substrate, and then implanting ions into the second nitride layer to generate compressive stress, and then etching the second nitride layer to form barrier nitride layers on the side walls of the first spacers. Because the barrier nitride has compressive stress, it is possible to prevent the movement of mobile ions, minimize influence on charge loss and charge gain in a flash memory device, and enhance a retention characteristic.

Abstract: An image sensor and a method of manufacturing the same are provided. A metal wiring layer is formed on a semiconductor substrate including a circuit region, and first conductive layers are formed on the metal layer separated by a pixel isolation layer. An intrinsic layer is formed on the first conductive layers, and a second conductive layer is formed on the intrinsic layer.

Abstract: Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A spacer layer may be formed as a compound insulating layer structure over the side wall of the gate pattern. A source/drain area may be formed over the semiconductor substrate at both sides of the control gate. An insulating layer located at the outermost of the spacer layer may be removed. A contact hole may be formed between the gate patterns by forming and patterning the interlayer insulating layer. A contact plug may be formed in the contact hole.

Abstract: A flash memory device and a method of manufacturing a flash memory device are provided. The flash memory device includes a gate region on a semiconductor substrate, spacers on sidewalls of the gate region, and a passivation layer between the semiconductor substrate and a portion of each spacer.

Abstract: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.

Abstract: Embodiments relater to a semiconductor device and a method of fabricating the same. A source/drain area may be formed by using the spacer having the dual structure of the oxide layer and nitride layer. After etching a part of the oxide layer, the salicide layer may be formed on the gate electrode and the source/drain area, and the spacer may be removed. The contact area may be ensured, so a higher degree of integration may be achieved.

Abstract: A flash memory device having a spacer of a gate region formed in an oxide-nitride-oxide (ONO) structure and a source/drain region formed using the ONO structure. The outermost oxide in the ONO structure is removed and an interlayer insulating film is formed to ensure sufficient space between the gate regions. Thus, it is possible to prevent a void from being generated in the interlayer insulating film and prevent a word line from being electrically connected to a drain contact for forming a bit line.

Abstract: A flash memory device with a system in package (SIP) structure and a fabricating method thereof are provided. In the semiconductor device of an embodiment, a flash memory device is formed by forming cell transistors and high voltage transistors on different wafers, and connecting each of vertically stacked chips in a via pattern. According to an embodiment, a device isolating layer and a device can be fabricated to be met with the features of the cell transistor which is not affected by the high voltage transistor, a gap fill margin of the device isolating device in forming the cell transistor is large, and the degree of integration is increased to improve yield. Also, the high voltage transistors in a driving circuit unit can be designed and fabricated without suffering from the effect of the cell transistor.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device can include a first chip having transistors of only the NMOS type, a second chip having transistors of only the PMOS type, and an interconnection electrically connecting the first and second chips to each other. By forming NMOS and PMOS transistors on separate chips, the total number of implant photo processes can be decreased, thereby reducing the fabrication cost.

Abstract: A semiconductor device, such as a positive channel metal-oxide semiconductor (PMOS) transistor, and a fabricating method thereof are provided. The semiconductor device includes: a gate insulation layer and a gate electrode, a semiconductor substrate, a spacer formed on side walls of the gate insulation layer and the gate electrode, a lightly doped drain (LDD) area formed on the semiconductor substrate at both sides of the gate electrode, a source/drain area formed on the semiconductor substrate at both sides of the gate electrode, and an oxide-nitride layer formed on the gate electrode and on the source/drain area.

Abstract: Disclosed herein is an ion implantation apparatus for use in manufacturing of a semiconductor device, which has a software program including an option for selecting a manipulator, enabling a time for beam tuning to be minimized. The ion implantation apparatus further includes a manipulator for extracting and focusing an ion source and an ion beam, a control block for controlling overall operation of the ion implantation apparatus and recognizing a newly installed manipulator, and a control window on which a selection menu is displayed, allowing recipe data to be selected on a screen. When installing a replacement manipulator, recipe data for the replacement manipulator can be selected to improve beam tuning set up time.

Abstract: A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.

Abstract: A method for manufacturing a semiconductor device including at least one of the following steps. Forming a first semiconductor substrate including a first conductive pattern. Adhering a second semiconductor including a second conductive pattern on the first semiconductor substrate using adhesive paste. Forming a through hole by patterning the first semiconductor substrate and the second semiconductor substrate. Forming a through electrode by depositing a barrier metal on the through hole and burying and planarizing metal materials.

Abstract: A device may include at least one of the following: A first substrate including a plurality of N-channel metal oxide semiconductor transistors, with the N-channel MOS transistors including an access transistor and a drive transistor. A second substrate including a plurality of P-channel metal oxide semiconductor transistors used as pull-up devices. A first connecting device formed on at least one of the first substrate and the second substrate to connect the plurality of N-channel metal oxide semiconductor transistors to the plurality of P-channel metal oxide semiconductor transistors, wherein the four N-channel metal oxide semiconductor transistors formed on the first substrate and the two P-channel metal oxide semiconductor transistors formed on the second substrate form the unit memory cell.

Abstract: Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 ?m. Ions are implanted into the pMOS region to form a p type well. A second mask is formed to shield the pMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 ?m. Ions are implanted into the nMOS region to form an n type well. A gate oxide film and a gate is formed over the semiconductor substrate. A low-concentration impurity may be implanted by using the gate as a mask. An LDD region may be formed. A sidewall spacer may be formed over both sidewalls of the gate. A high-concentration impurity is implanted by using the sidewall spacer as a mask, forming a source/drain region.

Abstract: A method is provided for forming a lightly-doped drain (LDD) area of a transistor by means of a single implant process. The method includes implanting a dopant under a process condition of an ;implantation energy of 10 KeV or less and a dose of 1.5×1014 to 3.0×1014 ions/cm2. The method makes it possible to simplify the process thereof, reduce the process time thereof, and improve the breakdown voltage of a device. The method can be used for 180 nm-grade or smaller flash memory.

Abstract: A semiconductor device and a fabricating method thereof are provided. Barrier patterns are formed between a gate and spacers, and between LDD regions and the spacers, thereby inhibiting impurities of the LDD regions from diffusing into the gate.