Abstract: A memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data and a control circuit configured to perform plural program loops for storing the data, each program loop including a program voltage application operation and a verification operation. During the respective program loop, the control circuit performs the verification operation for an N target level, an N?1 target level lower than the N target level, and an N+1 higher than the N target level, in response to the program voltage application operation for the N target level. When a quantity of non-volatile memory cells having threshold voltages over the N+1 target level satisfies a preset criterion, the control circuit skips a next verification for a target level lower than the N+1 target level, in response to a next program voltage application operation for the N+1 target level.

Abstract: Provided herein may be a memory device capable of completing program operations for multiple pages in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation and a second program operation and control logic configured to control the peripheral circuit to receive least significant bit (LSB) page data of a page adjacent to a selected page, center significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page from a memory controller, and program the LSB page data of the page adjacent to the page adjacent to the selected page and to obtain LSB page data from the selected page, previously stored in the selected page, and program the LSB page data, the CSB page data and the MSB page data of the selected page to the selected page.

Abstract: A memory device having an improved operation speed includes: a memory cell; a page buffer connected to the memory cell through a bit line; and a program operation controller for controlling an operation of the page buffer. The page buffer includes: a bit line voltage supply for providing a precharge voltage to the bit line; a sensing node voltage supply for providing a sensing node precharge voltage to a sensing node connected to the bit line; a first latch for storing first verify data; a sensing node connector for releasing connection between the bit line and the sensing node, after the first verify data is stored; and a second latch for storing second verify data determined according to the voltage of the sensing node, after the connection between the bit line and the sensing node is released.

Abstract: Provided herein may be a memory device capable of completing a foggy-fine program operation in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation on a page adjacent to a selected page among the plurality of pages, and perform a second program operation on the selected page and control logic configured to control the peripheral circuit, during the first program operation, to successively receive least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data from a memory controller, and program the LSB page data to the page adjacent to the selected page and during the second program operation, to program the LSB page data programmed to the page adjacent to the selected page, the CSB page data and the MSB page data to the selected page.

Abstract: A memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data and a control circuit configured to perform plural program loops for storing the data, each program loop including a program voltage application operation and a verification operation. During the respective program loop, the control circuit performs the verification operation for an N target level, an N?1 target level lower than the N target level, and an N+1 higher than the N target level, in response to the program voltage application operation for the N target level. When a quantity of non-volatile memory cells having threshold voltages over the N+1 target level satisfies a preset criterion, the control circuit skips a next verification for a target level lower than the N+1 target level, in response to a next program voltage application operation for the N+1 target level.

Abstract: A memory device having an improved operation speed includes: a memory cell; a page buffer circuit connected to the memory cell through a bit line; and a program operation controller for controlling an operation of the page buffer circuit. The page buffer circuit includes: a bit line voltage supply for providing a precharge voltage to the bit line; a sensing node voltage supply for providing a sensing node precharge voltage to a sensing node connected to the bit line; a first latch for storing first verify data; a sensing node connector for releasing connection between the bit line and the sensing node, after the first verify data is stored; and a second latch for storing second verify data determined according to the voltage of the sensing node, after the connection between the bit line and the sensing node is released.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops.

Abstract: Provided herein may be a memory device capable of completing a foggy-fine program operation in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation on a page adjacent to a selected page among the plurality of pages, and perform a second program operation on the selected page and control logic configured to control the peripheral circuit, during the first program operation, to successively receive least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data from a memory controller, and program the LSB page data to the page adjacent to the selected page and during the second program operation, to program the LSB page data programmed to the page adjacent to the selected page, the CSB page data and the MSB page data to the selected page.

Abstract: Provided herein may be a memory device capable of completing program operations for multiple pages in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation and a second program operation and control logic configured to control the peripheral circuit to receive least significant bit (LSB) page data of a page adjacent to a selected page, center significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page from a memory controller, and program the LSB page data of the page adjacent to the page adjacent to the selected page and to obtain LSB page data from the selected page, previously stored in the selected page, and program the LSB page data, the CSB page data and the MSB page data of the selected page to the selected page.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops.

Abstract: The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.

Abstract: The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.

Abstract: The present disclosure relates to a technology which effectively absorbs a gear shifting impact by sequential fastening discs or plates to one another by a friction element. The friction element includes: a multi-plate disc set having discs and/or plates, and a fastening device having springs. In particular, the springs may start to be compressed from a spring having the smallest spring constant to a spring having a greater spring constant so as to sequentially fasten the discs and plates to one another so that the amount of a change in a stroke of a piston with respect to a change in an operation force of the piston is sequentially reduced.

Abstract: A method of operating a semiconductor device includes selecting one of a plurality of memory cell blocks included in a memory cell array, programming even-numbered memory cells coupled to a selected word line among the word lines of the selected memory cell block, programming odd-numbered memory cells coupled to the selected word line, programming odd-numbered memory cells coupled to a next word line adjacent to the selected word line, and programming even-numbered memory cells coupled to the next word line, wherein the programming is repeated until programming on selected memory cells coupled to all the word lines of the selected memory cell block is completed.

Abstract: A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.

Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.

Abstract: A method of operating a nonvolatile memory device includes programming first memory cells to make threshold voltages of the first memory cells to reach a verification voltage determined based on program data of second memory cells to be programmed, and programming the second memory cells.

Abstract: A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.

Abstract: A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the first voltage. The second voltage generator operates to change the first voltage according to change of temperatures thereby generating a third voltage. The voltage transmission unit operates to transmit the second voltage or the third voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal.

Abstract: A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the first voltage. The second voltage generator operates to change the first voltage according to change of temperatures thereby generating a third voltage. The voltage transmission unit operates to transmit the second voltage or the third voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal.