Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A method for fabricating the three dimensional (3D), non-volatile memory (NVM) device includes: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of first material layers which are alternately stacked; forming at least one channel hole penetrating through the stack structure; forming a second material layer along the at least one channel hole; trimming a surface of the second material layer; oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer; and forming a charge storage layer and a tunnel insulating layer over the charge blocking layer.

Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A method for fabricating the three dimensional (3D), non-volatile memory (NVM) device includes: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of first material layers which are alternately stacked; forming at least one channel hole penetrating through the stack structure; forming a second material layer along the at least one channel hole; trimming a surface of the second material layer; oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer; and forming a charge storage layer and a tunnel insulating layer over the charge blocking layer.

Abstract: A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.

Abstract: A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.

Abstract: A plasma display panel is provided having a first substrate and a second substrate facing the first substrate with an interval therebetween. An address electrode extends in a first direction on the first substrate. A dielectric layer is on the first substrate covering the address electrode. One or more barrier ribs are on the dielectric layer to define a discharge cell in relation to the address electrode. A phosphor layer is in the discharge cell. A first electrode and a second electrode extend in a second direction on the second substrate corresponding to the discharge cell. The second direction crosses the first direction. The dielectric layer includes a flat surface facing the discharge cell.

Abstract: An electron emission device includes a substrate, a cathode electrode located on the substrate and having a first opening, the cathode electrode including a material that substantially blocks ultraviolet rays, an electron emission region that is located in the first opening and adapted to emit electrons, a gate electrode that is electrically insulated from the cathode electrode, the gate electrode including a material that substantially blocks ultraviolet rays, and a plurality of insulation layers located between the cathode and gate electrodes. The plurality of insulation layers includes first and second insulation layers adjacent to each other. The first insulation layer has a first etching rate that is different from a second etching rate of the second insulation layer.