Abstract: An organic light emitting device includes an organic light emitting diode on a substrate and an encapsulation layer covering the organic light emitting diode. The encapsulation layer includes an organic layer, an inorganic layer on the organic layer, and an intermixing region between the organic layer and the inorganic layer, the organic layer includes an organic material, the inorganic layer includes an inorganic material, and the intermixing region includes the organic material and the inorganic material.

Abstract: An organic light emitting display includes a substrate, an OLED including an anode electrode, a cathode electrode and an organic thin film formed between the anode electrode and the cathode electrode, a reflective layer on the OLED, the reflective layer comprising a laminated first material and second material, the first material and the second material having different refractive indices, and an encapsulation layer on the reflective layer, the encapsulation layer comprising at least one of organic thin film and inorganic thin film.

Abstract: Disclosed is an organic light emitting display and a method for manufacturing the same capable of preventing external moisture or oxygen from being penetrated into an organic light emitting diode. In particular, disclosed is an organic light emitting display comprising an organic light emitting diode array comprising a light emitting diode formed over a substrate and an organic emission layer between a first electrode and a second electrode, a sealing cover comprising at least one organic film and at least one inorganic film, and a sealing material formed along an edge of the sealing cover for sealing a boundary of the substrate and the sealing cover and a boundary of the organic film and the inorganic film of the sealing cover.

Abstract: An organic light emitting display device and a manufacturing method of forming an inorganic layer formed on the top of the sealing film with nitride are disclosed. In one embodiment, the organic light emitting display device includes: i) a substrate on which at least one organic light emitting diode is formed and ii) a sealing film stacked with at least one organic film and inorganic film and sealing the organic light emitting diode, wherein the top of the sealing film is formed of an inorganic film formed of nitride.

Abstract: A method of aligning a substrate includes forming a first alignment hole in the substrate, preparing a mask with a second alignment hole narrower than the first alignment hole, modifying a surface reflectance around either the first alignment hole or the second alignment hole to form a treatment region, positioning the mask below the substrate, such that the first and second alignment holes overlap, and operating a sensor unit above the first alignment hole to examine alignment of the first and second alignment holes.

Abstract: A multi-way set-associative cache memory is configured to operate only with those ways of the tag and data memories that operate normally, and excludes those ways of the tag and data memories that are determined to be incurably defective. By reducing the size of the cache memory to exclude the defective cells, the present invention is capable of preventing scrapping or discarding of the entire high-priced processor chip in which CPU and cache memory are integrated into a single chip.

Abstract: A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select one of sets while plural sets are active by a row address. The simplified structure of the present cache memory reduces power consumption by the rate of 1/N (N is the number of sets).

Abstract: A multi-way set-associative cache memory is configured to operate only with those ways of the tag and data memories that operate normally, and excludes those ways of the tag and data memories that are determined to be incurably defective. By reducing the size of the cache memory to exclude the defective cells, the present invention is capable of preventing scrapping or discarding of the entire high-priced processor chip in which CPU and cache memory are integrated into a single chip.

Abstract: A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select one of sets while plural sets are active by a row address. The simplified structure of the present cache memory reduces power consumption by the rate of 1/N (N is the number of sets).

Abstract: A synchronous memory device includes a late write mode of operation, and includes a memory cell array storing data information. The synchronous memory device comprises a write-in command detector, a data input control signal generator, first and second latch circuits, and a multiplexer. The write-in command detector generates a first flag signal indicating that write-in command is applied to the memory device, and generates a second flag signal indicating that the write-in command is received during successive clock cycles. The data input control signal generator, in response to the first flag signal, sequentially generates data input control signals synchronized with a clock signal. The first latch circuit sequentially latches write-in data from external sources in response to the data input control signals, and the second latch circuit latches data latched in the first latch circuit in response to at least one of the data input control signals.

Abstract: Alternative methods for detecting a short-circuit between signal lines in an electrically erasable and programmable nonvolatile semiconductor memory device use circuitry for detecting short-circuited signal lines. One method includes the steps of: floating first and second signal lines in response to another external input; simultaneously forming an electrical path between the first and second signal lines and each test pad; and determining whether a current path is formed between the test pads, for detecting any short-circuit between the first and second signal lines. Another method includes the steps of: floating the first and second signal lines in response to another external input; simultaneously forming the electrical path between the first signal line and the test pad while discharging the second signal line to the reference potential; and determining whether a current path is formed from the test pad to the reference potential, for detecting any short-circuit between the first and second signal lines.