Patents by Inventor Jin Ho ON

Jin Ho ON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190833
    Abstract: Disclosed herein is a method for moving magic states through boundary extension in a rotated surface code. The method for moving magic states includes identifying logical data and an ancilla qubit constituting a logical qubit block, and an available magic state logical qubit from a magic state storage space, identifying a type of a movement operation and a bending location during movement by analyzing a path through which the magic state logical qubit is moved to a location of a desired logical ancilla qubit, defining a movement operation process based on boundary extension in consideration of the type of the movement operation and the bending location during the movement, and moving the magic state logical qubit to the location of the logical ancilla qubit in conformity with the movement operation process.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 12, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang-Min LEE, Soo-Cheol OH, Young-Chul KIM, Chei-Yol KIM, Jin-Ho ON, Eun-Young CHO, Ki-Sung JIN, GYU-IL CHA
  • Publication number: 20250061361
    Abstract: Disclosed herein is an apparatus and method for executing a magic state distillation circuit in a logical qubit quantum system. The apparatus outputs a distilled magic state |Y>L by executing a magic state |Y>L distillation circuit in which multiple multi-target CNOT operations are performed in parallel and outputs a distilled magic state |A>L by executing a magic state |A>L distillation circuit in which multiple multi-target CNOT operations are performed in parallel. The magic state |Y>L distillation circuit is configured with three code blocks, code blocks 1 and 2 being configured with multiple multi-target CNOT operations and code block 3 being configured with SL operations and measurement operations, and the magic state |A>L distillation circuit is configured with three code blocks, code blocks 1 and 2 being configured with multiple multi-target CNOT operations and code block 3 being configured with TL+ operations and measurement operations.
    Type: Application
    Filed: August 13, 2024
    Publication date: February 20, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo-Cheol OH, Young-Chul KIM, Chei-Yol KIM, Jin-Ho ON, Sang-Min LEE, Eun-Young CHO, Ki-Sung JIN, Gyu-Il CHA
  • Publication number: 20240303523
    Abstract: Disclosed herein are an apparatus and method for performing a fault-tolerant logical Hadamard gate operation. The apparatus is configured to perform a transversal logical Hadamard (H) operation of defining a logical quantum state and logical operators of a Hadamard-transformed logical qubit on a logical qubit of a prepared encoding flavor having an arbitrary quantum state, deform a boundary of the logical qubit while maintaining the logical quantum state using a boundary deformation technology, and perform an automatic flip of transforming a flavor of the logical qubit by flipping a rotated surface code while maintaining the logical quantum state and the definition of logical operators.
    Type: Application
    Filed: November 21, 2023
    Publication date: September 12, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang-Min LEE, Young-Chul KIM, Soo-Cheol OH, Jin-Ho ON, Ki-Sung JIN, Gyu-Il CHA
  • Publication number: 20240127094
    Abstract: Disclosed herein are a logical qubit execution apparatus and method. The logical qubit execution apparatus may be configured to execute, by a logical execution layer, a quantum circuit including requested logical qubits using a lattice surgery operation, generate, by the logical execution layer, measurement results of the logical qubits by combining measurement results of logical Pauli frames, generate, by a physical execution layer, a physical qubit circuit by converting a logical qubit operation corresponding to the measurement results of the logical qubits into a physical qubit operation, and measure, by the physical execution layer, results of an operation on physical Pauli frames by executing the physical qubit circuit.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 18, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho ON, Chei-Yol KIM, Soo-Cheol OH, Sang-Min LEE, Gyu-Il CHA
  • Patent number: 11762733
    Abstract: Disclosed is a quantum computing system including a first quantum chip including first physical qubits, a second quantum chip including second physical qubits, and a management device. The management device includes a physical qubit layer that manages physical qubit mapping including information about physical channels between first and second physical qubits, an abstraction qubit layer that manages abstraction qubit mapping including information about abstraction qubits and abstraction channels between the abstraction qubits based on the physical qubit mapping, a logical qubit layer that divides the abstraction qubits into logical qubits and to manage logical qubit mapping including information about logical channels between the logical qubits, based on the abstraction qubit mapping, and an application qubit layer that allocates at least one logical qubit corresponding to a qubit request received from a quantum application program based on the logical qubit mapping.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: September 19, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Ho On, Chei-Yol Kim, SooCheol Oh, Gyuil Cha, Hee-Bum Jung
  • Publication number: 20230129967
    Abstract: A quantum computing system according to an embodiment of the present disclosure includes a logical qubit quantum compiler configured to receive a specific quantum code and to output a quantum kernel based on a quantum basic operation command, a logical qubit quantum kernel executor configured to generate a plurality of physical qubit quantum commands based on the quantum kernel, and a physical qubit quantum system configured to receive the physical qubit quantum command and to perform a physical quantum operation.
    Type: Application
    Filed: August 31, 2022
    Publication date: April 27, 2023
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Soo Cheol OH, Chei Yol KIM, Jin Ho ON, Sang Min LEE, Gyu Il CHA
  • Publication number: 20220164253
    Abstract: Disclosed is a quantum computing system including a first quantum chip including first physical qubits, a second quantum chip including second physical qubits, and a management device. The management device includes a physical qubit layer that manages physical qubit mapping including information about physical channels between first and second physical qubits, an abstraction qubit layer that manages abstraction qubit mapping including information about abstraction qubits and abstraction channels between the abstraction qubits based on the physical qubit mapping, a logical qubit layer that divides the abstraction qubits into logical qubits and to manage logical qubit mapping including information about logical channels between the logical qubits, based on the abstraction qubit mapping, and an application qubit layer that allocates at least one logical qubit corresponding to a qubit request received from a quantum application program based on the logical qubit mapping.
    Type: Application
    Filed: September 10, 2021
    Publication date: May 26, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jin Ho ON, Chei-Yol KIM, SooCheol OH, GYUIL CHA, Hee-Bum JUNG
  • Publication number: 20220164496
    Abstract: Disclosed is an operating method of a surface code-based quantum simulation device including physical qubit storage, which includes storing initialized entanglement states of logical qubits corresponding to different distances, receiving a surface code-based initialization request corresponding to a specific distance, and storing an initialized entanglement state of a logical qubit corresponding to the specific distance from among the initialized entanglement states of the logical qubits corresponding to the different distances in the physical qubit storage.
    Type: Application
    Filed: August 24, 2021
    Publication date: May 26, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: SooCheol OH, Chei-Yol KIM, Jin Ho ON, GYUIL CHA, Hee-Bum JUNG
  • Patent number: 11175960
    Abstract: A method and apparatus are disclosed which relate generally to worker-scheduling technology in a serverless cloud-computing environment, and more particularly, to technology that allocates workers for executing functions on a micro-function platform which provides a function-level micro-service. The method and apparatus process a worker allocation task in a distributed manner as two-step pre-allocation schemes before a worker allocation request occurs, and pre-allocates workers required for a service using a function request period and a function execution time, thus minimizing scheduling costs incurred by worker allocation requests.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 16, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Ho Kim, Chei-Yol Kim, Jin-Ho On, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10983835
    Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 20, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chei-Yol Kim, Young-Ho Kim, Jin-Ho On, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10977007
    Abstract: An apparatus and method for executing a function. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors, and the at least one program is configured to determine whether it is possible to reengineer a user function source using interface description language (IDL) code, to generate a reengineered function source by reengineering the user function source, and to execute the reengineered function source.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 13, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho On, Young-Ho Kim, Chei-Yol Kim, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10783015
    Abstract: Disclosed herein are an apparatus and method for providing long-term function execution in a serverless environment. The method for providing long-term function execution in a serverless environment is performed by an apparatus for providing long-term function execution in a serverless environment, and includes registering a long-term function execution proxy when a long-term execution request is received from a client, allocating a long-term function executor corresponding to the long-term execution request, executing, by the long-term function execution proxy, a long-term function using the allocated long-term function executor, and storing execution results of the long-term function.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: September 22, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho On, Ki-Young Kim, Gyu-Il Cha
  • Publication number: 20200183746
    Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.
    Type: Application
    Filed: October 21, 2019
    Publication date: June 11, 2020
    Inventors: Chei-Yol KIM, Young-Ho KIM, Jin-Ho ON, Su-Min JANG, Gyu-Il CHA
  • Publication number: 20200183744
    Abstract: A worker-scheduling method in a cloud-computing system and an apparatus for the same. The worker-scheduling method includes performing a first load-distribution operation of pre-creating template workers so as to process worker execution preparation loads in a distributed manner before a worker allocation request for function execution occurs, predicting a number of workers to be pre-allocated in consideration of variation in a worker allocation request period for each function, and performing a second load distribution operation of pre-allocating ready workers by performing worker upscaling on as many template workers as the number of workers to be pre-allocated.
    Type: Application
    Filed: September 26, 2019
    Publication date: June 11, 2020
    Inventors: Young-Ho KIM, Chei-Yol KIM, Jin-Ho ON, Su-Min JANG, Gyu-Il CHA
  • Publication number: 20200183657
    Abstract: An apparatus and method for executing a function. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors, and the at least one program is configured to determine whether it is possible to reengineer a user function source using interface description language (IDL) code, to generate a reengineered function source by reengineering the user function source, and to execute the reengineered function source.
    Type: Application
    Filed: September 19, 2019
    Publication date: June 11, 2020
    Inventors: Jin-Ho ON, Young-Ho KIM, Chei-Yol KIM, Su-Min JANG, Gyu-Il CHA
  • Publication number: 20190179684
    Abstract: Disclosed herein are an apparatus and method for providing long-term function execution in a serverless environment. The method for providing long-term function execution in a serverless environment is performed by an apparatus for providing long-term function execution in a serverless environment, and includes registering a long-term function execution proxy when a long-term execution request is received from a client, allocating a long-term function executor corresponding to the long-term execution request, executing, by the long-term function execution proxy, a long-term function using the allocated long-term function executor, and storing execution results of the long-term function.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Jin-Ho ON, Ki-Young KIM, Gyu-Il CHA
  • Publication number: 20180284870
    Abstract: Disclosed herein are a method and apparatus for automatically determining the energy efficiency and the energy rating of a target device. An apparatus for measuring energy efficiency may automatically boot and configure a target device with regard to the energy efficiency of the target device, measure the energy efficiency of the target device, and determine the energy rating of the target device. The apparatus may provide a boot image and a workload to the target device. Also, the apparatus may control the workload that is executed in the target device. The apparatus may collect information about the execution of the workload from the target device, measure the energy efficiency of the target device using the information, and determine the energy rating of the target device.
    Type: Application
    Filed: January 8, 2018
    Publication date: October 4, 2018
    Inventor: Jin-Ho ON
  • Patent number: 10007291
    Abstract: An apparatus and method for performing the dynamic frequency control of a central processing unit (CPU). The apparatus for performing the dynamic frequency control of a central processing unit (CPU) includes a frequency setting unit, a latency measurement unit, a frequency adjustment unit, and a control unit. The frequency setting unit sets optimum frequency using the measured amount of load. The latency measurement unit measures scheduler execution information. The frequency adjustment unit adjusts the optimum frequency using the scheduler execution information. The control unit incorporates the adjusted optimum frequency into a CPU.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 26, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Jin-Ho On
  • Patent number: 9760154
    Abstract: Provided is a method of dynamically controlling power in a multicore environment including a multicore processor which includes a plurality of cores and a scheduler. The method includes determining whether a management policy is set, collecting frequency change information used to change frequencies of the plurality of cores when it is determined that the management policy is set, calculating an average load of each core on a basis of the frequency change information, calculating an average frequency of each core according to the calculated average load of each core, comparing the average frequency of each core and a predetermined threshold value, and setting a next frequency of each core according to the comparison result.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: September 12, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Ik Jun, Baik Song An, Jin Ho On, Young Choon Woo, Wan Choi
  • Publication number: 20170235356
    Abstract: An electronic device includes a system bus, a hardware including a plurality of physical devices connected to the system bus, and a power controller connected to the system bus to collect through the system bus state information about each of the plurality of physical devices, select a specific category corresponding to the collected state information by using a previously constructed decision-making tree model, and control an operation of each of the plurality of physical devices according to a power reduction policy mapped to the selected specific category.
    Type: Application
    Filed: June 16, 2016
    Publication date: August 17, 2017
    Inventor: Jin Ho ON