Abstract: Disclosed herein are an apparatus and method for adaptively accelerating a BLAS operation based on a GPU. The apparatus for adaptively accelerating a BLAS operation based on a GPU includes a BLAS operation acceleration unit for setting optimal OpenCL parameters using machine-learning data attribute information and OpenCL device information and for creating a kernel in a binary format by compiling kernel source code; an OpenCL execution unit for creating an OpenCL buffer for a BLAS operation using information about an OpenCL execution environment and the optimal OpenCL parameters and for accelerating machine learning in an embedded system in such a way that a GPU that is capable of accessing the created OpenCL buffer performs the BLAS operation using the kernel, and an accelerator application unit for returning the result of the BLAS operation to a machine-learning algorithm.

Abstract: Disclosed herein are an apparatus and method for adaptively accelerating a BLAS operation based on a GPU. The apparatus for adaptively accelerating a BLAS operation based on a GPU includes a BLAS operation acceleration unit for setting optimal OpenCL parameters using machine-learning data attribute information and OpenCL device information and for creating a kernel in a binary format by compiling kernel source code; an OpenCL execution unit for creating an OpenCL buffer for a BLAS operation using information about an OpenCL execution environment and the optimal OpenCL parameters and for accelerating machine learning in an embedded system in such a way that a GPU that is capable of accessing the created OpenCL buffer performs the BLAS operation using the kernel, and an accelerator application unit for returning the result of the BLAS operation to a machine-learning algorithm.

Abstract: Disclosed herein are an apparatus and method for controlling a governor based on a heterogeneous multicore system. The apparatus includes a heterogeneous core cluster unit for running any one of a first core cluster for high-performance operation and a second core cluster for low-power operation by switching therebetween; a governor-setting unit for generating operation setting information of a governor for controlling operation of the first core cluster and second core cluster; and a governor control unit for controlling operation of one or more governors based on the operation setting information.

Abstract: Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.

Abstract: A cone type venturi integrated valve device includes a main body, a venturi cone, a valve path, and valves disposed in the valve path. The main body has a venturi path which penetrates though the main body in a horizontal direction and a hole which penetrates through the main body from the venturi path to a bottom of the main body, wherein the venturi path includes an inlet, an outlet, a first pressure point P1 at a distance from the inlet, and a second pressure point P2 at a distance from the outlet. The venturi cone is mounted between the first pressure point P1 and the second pressure point P2 in the venturi path of the main body. The venturi cone has a fixing leg bent downward and a bent end of the fixing leg is inserted into the hole of the main body and attached by welding.

Abstract: Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.

Abstract: Provided is a valve device into which a cone type venturi for a flow measurement and valves are integrated. According to the present invention, the venturi cone is formed in venturi path in the lower portion of the main body, and then valve path is formed thereafter. According to the present invention, efforts for adjusting heights between both of pressure taps during connecting of valves and flow measurement parts are not required and installation time and costs of installation could be decreased drastically. Also, the possibilities of leakage as well as manufacturing costs also could be reduced by integrating valves and flow measurement parts into a one-body valve device.