Patents by Inventor Jin-hong Park

Jin-hong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006190
    Abstract: A method of manufacturing a semiconductor device includes forming a channel layer on a substrate, forming a mask on the channel layer, surface-treating an exposed surface of the channel layer exposed from the mask, forming an electrode on the exposed surface of the channel layer, and removing the mask. The channel layer includes a two-dimensional material, and the surface-treating of the exposed surface of the channel layer includes surface-treating the exposed surface of the channel layer with HCl.
    Type: Application
    Filed: March 6, 2023
    Publication date: January 4, 2024
    Applicants: SAMSUNG ELECTRONICS CO., LTD, RESEARCH & BUSINESS FOUNDATION OF SUNGKYEUNGAM UNIVERSITY
    Inventors: Jin-Hong PARK, Hogeun AHN, BoReum LEE, Sunguk JANG, Jiwan KOO, Seunghwan SEO
  • Publication number: 20230418161
    Abstract: Organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that in a first aspect comprise a crosslinker component that comprises a structure of the following Formula (I):
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Eui-Hyun Ryu, Jin Hong Park, You Rim Shin, Ji-Hon Kang, Jung-June Lee, Jae-Bong Lim
  • Patent number: 11822248
    Abstract: Organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that in a first aspect comprise a crosslinker component that comprises a structure of the following Formula (I):
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: November 21, 2023
    Assignee: ROHM AND HAAS ELECTRONIC MATERIALS KOREA LTD.
    Inventors: Eui-Hyun Ryu, Jin Hong Park, You Rim Shin, Ji-Hon Kang, Jung-June Lee, Jae-Bong Lim
  • Publication number: 20230245887
    Abstract: Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.
    Type: Application
    Filed: January 5, 2023
    Publication date: August 3, 2023
    Applicants: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sang-Yong PARK, Jin-Hyuk KIM, Jin-Hong PARK, Sejin KYUNG
  • Patent number: 11670714
    Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 6, 2023
    Inventors: Kilsu Jung, Jin-Hong Park, Keun Heo, Sungjun Kim
  • Patent number: 11588066
    Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 21, 2023
    Assignee: The Board of Trustees of the Leland Stanford Junior Univesity
    Inventors: Koosha Nassiri Nazif, Raisul Islam, Jin-Hong Park, Krishna C. Saraswat
  • Patent number: 11567409
    Abstract: A polymer comprising a first repeating unit including an amino group protected by an alkoxycarbonyl group; a second repeating unit including a nucleophilic group; and a third repeating unit including a crosslinkable group, wherein the first repeating unit, the second repeating unit, and the third repeating unit are different from each other.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: January 31, 2023
    Assignee: ROHM AND HAAS ELECTRONIC MATERIALS KOREA LTD.
    Inventors: Jung June Lee, Suwoong Kim, Min Kyung Jang, Jin Hong Park, Jae Hwan Sim, Jae Bong Lim
  • Publication number: 20220397827
    Abstract: A photoresist underlayer composition, comprising: a first polymer comprising a crosslinkable group; a second polymer comprising: a first repeating unit comprising a repeating unit comprising a photoacid generator, and a second repeating unit comprising a hydroxy-substituted C1-30 alkyl group, a hydroxy-substituted C3-30 cycloalkyl group, or a hydroxy-substituted C6-30 aryl group; an acid catalyst; and a solvent.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 15, 2022
    Inventors: Jung June Lee, Jae Hwan Sim, Suwoong Kim, Jin Hong Park, Bhooshan Popere
  • Publication number: 20220384500
    Abstract: A photodetector includes a gate electrode extending in a first direction, a ferroelectric layer on the gate electrode and maintaining a state of polarization formed by a gate voltage applied to the gate electrode, a light absorbing layer on the ferroelectric layer and extending in a second direction intersecting the gate electrode, the light absorbing layer including a two-dimensional (2D) material of a layered structure, a source electrode on the ferroelectric layer and connected to a first end of the light absorbing layer, and a drain electrode on the ferroelectric layer and connected to the a second end of the light absorbing layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: December 1, 2022
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sungjun KIM, Jin-Hong PARK, Sunghun LEE, Keun HEO
  • Patent number: 11500291
    Abstract: New composition and methods are provided that include antireflective compositions that can exhibit enhanced etch rates in standard plasma etchants. Preferred antireflective coating compositions of the invention have decreased carbon content relative to prior compositions.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 15, 2022
    Assignee: ROHM AND HAAS ELECTRONIC MATERIALS KOREA LTD.
    Inventors: Jung-June Lee, Jae-Yun Ahn, You-Rim Shin, Jin-Hong Park, Jae-Hwan Sim
  • Patent number: 11502129
    Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: November 15, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Sungjoo Lee, Jae Hyeok Ju, Jin-Hong Park, Sungpyo Baek
  • Patent number: 11489041
    Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 1, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Kil Su Jung, Keun Heo, Sung Jun Kim
  • Patent number: 11437572
    Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Kil Su Jung, Keun Heo
  • Publication number: 20220271057
    Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.
    Type: Application
    Filed: February 7, 2022
    Publication date: August 25, 2022
    Applicant: RESEARCH AND BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sang-Yong PARK, Jin-Hong PARK, Sungjoo LEE
  • Publication number: 20220223630
    Abstract: A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 14, 2022
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Jin Hong PARK, Jae Woong CHOI, Je Jun LEE, Ju Hee LEE
  • Patent number: 11362224
    Abstract: Disclosed is a photodetector in which a plurality of conductive stripes spaced apart from each other are bonded onto a two-dimensional semiconductor thin-film, and a pitch between adjacent conductive stripes is controlled to selectively adjust a plasmonic resonance wavelength zone, such that the photodetector has a high absorbance and a wide detection zone at the same time. Further, a manufacturing method thereof is disclosed. The photodetector includes a semiconductor thin-film; and a plurality of conductive stripes bonded onto the semiconductor thin-film and extending in a parallel manner to each other and spaced apart from each other.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 14, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Sung Joo Lee, Jae Ho Jeon, Seung Hyuk Choi, Jin Hong Park
  • Patent number: 11329169
    Abstract: A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 10, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin-Hong Park, Jae-Woong Choi, Kwan-Ho Kim, Maksim Andreev
  • Publication number: 20220093803
    Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.
    Type: Application
    Filed: June 3, 2021
    Publication date: March 24, 2022
    Applicants: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Kilsu JUNG, Jin-Hong PARK, Keun HEO, Sungjun KIM
  • Patent number: 11262656
    Abstract: Organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that comprise that a blend of two or more resins, where one resin has epoxy groups either pendant or fused to the polymer backbone. Preferred coating compositions include: 1) a first resin that comprises one or more epoxy reactive groups; and 2) a crosslinker resin that is distinct from the first resin and comprises epoxy groups.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 1, 2022
    Assignee: Rohm and Haas Electronic Materials Korea Ltd.
    Inventors: Jae Hwan Sim, Hye-Won Lee, Eunhye Cho, Jung Kyu Jo, Jin Hong Park, Eui Hyun Ryu, Jae-Bong Lim
  • Publication number: 20210359150
    Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.
    Type: Application
    Filed: November 5, 2019
    Publication date: November 18, 2021
    Inventors: Koosha Nassiri Nazif, Raisul Islam, Jin-Hong Park, Krishna C. Saraswat