Abstract: A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

Abstract: What is discussed is an interconnection member including (a) a main cable made of a flexible flat cable (FFC) including copper wires, (b) terminal parts branched from the main cable and electrically connected to at least one of the copper wires of the main cable, (c) a connecting part formed on one-side end of the main cable, and electrically and mechanically connected to a PCB and (d) at least one temperature sensing part branched from the main cable, wherein the at least one temperature sensing part comprises a first extending part extending from the main cable while sharing at least one copper wire of the copper wires of the main cable and a ceramic thermistor disposed on an end of the first extending part while being electrically connected to the first extending part.

Abstract: A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

Abstract: A semiconductor device includes a substrate. A first channel pattern is disposed on the substrate. The first channel pattern includes a first side and a second side opposite to each other in a first direction. A first gate electrode is disposed on the first side of the first channel pattern. A first source/drain electrode is disposed on the first side of the first channel pattern. A second source/drain electrode is disposed on the second side of the first channel pattern. The first gate electrode overlaps the second source/drain electrode in the first direction.

Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes forming a channel layer on a substrate, forming a mask on the channel layer, surface-treating an exposed surface of the channel layer exposed from the mask, forming an electrode on the exposed surface of the channel layer, and removing the mask. The channel layer includes a two-dimensional material, and the surface-treating of the exposed surface of the channel layer includes surface-treating the exposed surface of the channel layer with HCl.

Abstract: Organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that in a first aspect comprise a crosslinker component that comprises a structure of the following Formula (I):

Abstract: Organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that in a first aspect comprise a crosslinker component that comprises a structure of the following Formula (I):

Abstract: Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.

Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.

Abstract: A polymer comprising a first repeating unit including an amino group protected by an alkoxycarbonyl group; a second repeating unit including a nucleophilic group; and a third repeating unit including a crosslinkable group, wherein the first repeating unit, the second repeating unit, and the third repeating unit are different from each other.

Abstract: A photoresist underlayer composition, comprising: a first polymer comprising a crosslinkable group; a second polymer comprising: a first repeating unit comprising a repeating unit comprising a photoacid generator, and a second repeating unit comprising a hydroxy-substituted C1-30 alkyl group, a hydroxy-substituted C3-30 cycloalkyl group, or a hydroxy-substituted C6-30 aryl group; an acid catalyst; and a solvent.

Abstract: A photodetector includes a gate electrode extending in a first direction, a ferroelectric layer on the gate electrode and maintaining a state of polarization formed by a gate voltage applied to the gate electrode, a light absorbing layer on the ferroelectric layer and extending in a second direction intersecting the gate electrode, the light absorbing layer including a two-dimensional (2D) material of a layered structure, a source electrode on the ferroelectric layer and connected to a first end of the light absorbing layer, and a drain electrode on the ferroelectric layer and connected to the a second end of the light absorbing layer.

Abstract: New composition and methods are provided that include antireflective compositions that can exhibit enhanced etch rates in standard plasma etchants. Preferred antireflective coating compositions of the invention have decreased carbon content relative to prior compositions.

Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.

Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

Abstract: A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode.