Patents by Inventor Jinhoon HYUN

Jinhoon HYUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device for correcting multi-phase clock signal
    Patent number: 10038433
    Abstract: A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 31, 2018
    Assignees: SK HYNIX INC., KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Jeong Cho, Soowon Kim, Jinhoon Hyun, Chanhui Jeong, Daehan Kwon
  • DEVICE FOR CORRECTING MULTI-PHASE CLOCK SIGNAL
    Publication number: 20170288656
    Abstract: A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.
    Type: Application
    Filed: March 23, 2017
    Publication date: October 5, 2017
    Inventors: Jeong CHO, Soowon KIM, Jinhoon HYUN, Chanhui JEONG, Daehan KWON