Abstract: The present invention relates to a heteroaryl derivative compound and a use thereof. Since the heteroaryl derivative of the present invention exhibits excellent inhibitory activity against EGFR, the heteroaryl derivative can be usefully used as a therapeutic agent for EGFR-associated diseases.

Abstract: The present invention relates to a surface treatment composition for forming a self-assembled coating layer which is easily coated and removed and a surface treatment method, where the self-assembled coating layer can be easily formed because of use of a compound having the hydroxyl groups as a diol are attached to an ortho position of a benzene ring and be removed by treatment of Al3+ or Fe3+. Thus, the surface can be reused by forming a new self-assembled coating layer, thereby making the surface treatment composition be applied to various researches and industrial fields of the self-assembly coating layer which are used for reduction in metal abrasion resistance, introduction of a chemical functional group for detecting a biomolecule, the surface hydrophilicity, introduction of an antifouling property to the surface, and the like.

Abstract: An arc discharge apparatus includes a body unit including a housing and a transmissive member fixed to the housing, the housing having a coolant inlet and a coolant outlet, and an electrode unit on the housing, the electrode unit including an anode and a cathode facing each other, wherein the anode includes a main body portion connected to the housing, an anode tip coupled to the main body portion, and a cooling line in the anode and in contact with an inner wall of the anode tip, the cooling line being connected to the coolant inlet and to the coolant outlet.

Abstract: The present invention relates to a surface treatment composition for forming a self-assembled coating layer which is easily coated and removed and a surface treatment method, where the self-assembled coating layer can be easily formed because of use of a compound having the hydroxyl groups as a diol are attached to an ortho position of a benzene ring and be removed by treatment of Al3+ or Fe3+. Thus, the surface can be reused by forming a new self-assembled coating layer, thereby making the surface treatment composition be applied to various researches and industrial fields of the self-assembly coating layer which are used for reduction in metal abrasion resistance, introduction of a chemical functional group for detecting a biomolecule, the surface hydrophilicity, introduction of an antifouling property to the surface, and the like.

Abstract: A vertical furnace is provided. The vertical furnace includes a chamber having a process space configured to receive substrates, a first exhaust passageway in fluidic communication with the process space, and a second exhaust passageway in fluidic communication with the process space and isolated from the first exhaust passageway; an injecting unit configured to inject a reaction gas into the process space; and an exhausting unit in fluidic communication with the first exhaust passageway and the second exhaust passageway and configured to provide the first exhaust passageway and the second exhaust passageway with an exhausting pressure.

Abstract: A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

Abstract: Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

Abstract: A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

Abstract: A method of forming a mask stack pattern and a method of manufacturing a flash memory device including an active area having rounded corners are provided. The method of manufacture including forming a mask stack pattern defining an active region, the mask stack pattern having a pad oxide layer formed on a semiconductor substrate, a silicon nitride layer formed on the pad oxide layer and a stack oxide layer formed on the silicon nitride layer, oxidizing a surface of the semiconductor substrate exposed by the mask stack pattern and lateral surfaces of the silicon nitride layer such that corners of the active region are rounded, etching the semiconductor substrate having an oxidized surface to form a trench in the semiconductor substrate, forming a device isolation oxide layer in the trench, removing the silicon nitride layer from the semiconductor substrate, and forming a gate electrode in a portion where the silicon nitride layer is removed.

Abstract: Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

Abstract: Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

Abstract: A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

Abstract: A method of manufacturing a semiconductor device in a process camber is disclosed. The method includes forming a preliminary dielectric layer including oxynitride on a substrate by performing a plasma oxidation treatment and a first plasma nitridation treatment, wherein the preliminary dielectric layer has a substantially uniform nitrogen concentration profile to a defined depth, and forming a dielectric layer from the preliminary dielectric layer by performing a second plasma nitridation treatment, wherein the nitrogen concentration of the dielectric layer is higher than that of the preliminary dielectric layer.

Abstract: Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

Abstract: The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.

Abstract: Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

Abstract: Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.

Abstract: Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.