Patents by Inventor Jin-Hwan Ham

Jin-Hwan Ham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11951162
    Abstract: The present invention provides an immunogenic composition comprising a Streptococcus pneumoniae polysaccharide-protein conjugate, comprising a capsular polysaccharide derived from one or more selected from the group consisting of serotypes 1, 2, 3, 4, 5, 6A, 6B, 7F, 8, 9N, 9V, 10A, 11A, 12F, 14, 15B, 17F, 18C, 19A, 19F, 20, 22F, 23F, and 33F, derived from Streptococcus pneumoniae; and one or 2 or more of carrier proteins conjugated to the respective capsular polysaccharide, and method of preparation thereof. Through one example of the present invention, an immunogenic composition for preventing or treating pneumococcal infection can be provided.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 9, 2024
    Assignee: SK BIOSCIENCE CO., LTD.
    Inventors: Hun Kim, Dong Soo Ham, Jin-Hwan Shin, Kyung-jun An, Sung-hyun Kim
  • Patent number: 8871105
    Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 28, 2014
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
  • Publication number: 20130237062
    Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Inventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
  • Patent number: 7494866
    Abstract: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: February 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa-Young Ko, Kyung-Rae Byun, Hyoung-Seub Rhie, Hee-Seok Kim, Jin-Hwan Ham, Suk-Ho Joo
  • Publication number: 20060273366
    Abstract: In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer. A hard mask structure is formed on the upper electrode layer. The hard mask structure includes a first hard mask and a second hard mask. An upper electrode, a ferroelectric layer pattern and a lower electrode are formed by partially etching the upper electrode layer, the ferroelectric layer and the lower electrode layer using the hard mask structure. The hard mask structure may prevent damage to the ferroelectric layer and may enlarge an effective area of the ferroelectric capacitor so that the ferroelectric capacitor may have enhanced electrical and ferroelectric characteristics.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 7, 2006
    Inventors: Hwa-Young Ko, Suk-Ho Joo, Byoung-Jae Bae, Hee-Seok Kim, Kyung-Rae Byun, Jin-Hwan Ham
  • Publication number: 20060237851
    Abstract: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.
    Type: Application
    Filed: April 14, 2006
    Publication date: October 26, 2006
    Inventors: Hwa-Young Ko, Kyung-Rae Byun, Hyoung-Seub Rhie, Hee-Seok Kim, Jin-Hwan Ham, Suk-Ho Joo