Abstract: A computer allows dynamic change of an instruction set during a real-time execution. The computer includes a CPU (Central Processing Unit) having an instruction fetch unit for fetching an instruction from a memory, an instruction decoding unit for generating a predetermined control code corresponding to the instruction fetched by the instruction fetch unit, and an arithmetic logic unit operated by the control code. The instruction decoding unit includes a basic instruction decoding unit for generating a control code for a basic instruction set; and a dynamic instruction decoding unit for generating another control code different from the control code corresponding to an instruction of the basic instruction set, or generating a control code corresponding to an instruction not existing in the basic instruction set. An instruction stored in the dynamic instruction decoding unit or a corresponding control code is configured to be changeable during execution in real time.

Abstract: A multiaccess circuit for a memory, which arbitrates a multiaccess operation and suspends a pipeline operation until requested data is generated in the memory when the multiaccess operation to the memory is occurred in a certain step of the pipeline, is capable of effectively performing the pipeline operation, and the multiaccess circuit for the memory carries out the multiaccess operation to the memory in accordance with its priority, thus the pipeline operation is performed without any collision.

Abstract: A pipeline stop circuit for an external memory access which is capable of effectively performing a pipeline operation by temporarily stopping a pipeline operation, which is being operated, until data are prepared in the memory accessed, when accessing an external memory or a slow internal memory.

Abstract: An arithmetic operating device and method for a digital signal processing (DSP) having a fixed bit number of input/output data bits significantly decreases the time conventionally spent on buffering in a converter. The device includes a sign bit extender for increasing number of sign bits an input data DATA.sub.-- IN, an adder for adding up the input data DATA.sub.-- IN which passed through the sign bit extender and a feedback data DATA.sub.-- ACC, an accumulator for accumulating a present output data and a previous output data from the adder, an overflow detector for detecting an overflow of the data DATA.sub.-- ACC outputted from the accumulator in accordance with an extended sign bit therein, and a saturation logic unit for converting the number of sign bits in the data DATA.sub.-- ACC outputted from the accumulator to an initial number of sign bits in the input data DATA.sub.-- IN in accordance with a signal OF outputted from the overflow detector, wherein the accumulator outputs the data DATA.sub.

Abstract: A Galois field multiplication method for a set of a finite number of elements which enables four arithmetical operations including an addition, a deduction, a multiplication and a division, and a multiplier utilizing the multiplication method are disclosed. The Galois field multiplication method easily realizes various Galois field multipliers by ANDing respective items of a multiplicand with a corresponding one of the items of a multiplier factor in a stepwise manner, rotating left values resulted from the AND operation at the previous step, exclusively ORing the respective values resulted from the rotation with the respective corresponding values resulted from the AND operation at the current step, and operating on the highest polynomial term generated at the previous step in accordance with a generated polynomial.