Abstract: Provided is a holographic optical element printing method using a tunable focus lens and a rotating mirror. According to an embodiment, a holographic printer includes: a first optical engine and a second optical engine configured to adjust a phase of an incident collimated beam and emit the collimated beam; and a first reduction optical system and a second reduction optical system configured to reduce the beam emitted from the first optical engine and the second optical engine and to allow the beam to enter a holographic material, wherein each of the first optical engine and the second optical engine includes: a rotating mirror configured to reflect while adjusting the phase of the incident collimated beam through rotation; and a tunable focus lens configured to refract while adjusting the phase of the incident collimated beam reflected from the rotating mirror through focus tuning.

Abstract: Provided is a cognitive experiment method for change in periphery region image quality for parameter determination of a foveated hologram. According to an embodiment, a cognitive experiment method for determining foveated image parameters includes: generating a foveated image which includes a foveal region and a periphery region while reducing image quality regarding the periphery region; displaying the generated foveated image; receiving an input of a response to image quality of the periphery region from a subject; and collecting information regarding appropriate image quality of the periphery region, based on the response inputted by the subject. Accordingly, in applying a foveated hologram generation algorithm for real-time reproduction, various parameters such as a boundary between a foveal region image and a periphery region image in a foveated hologram, and a degree of quality degradation of the periphery region image may be appropriately determined through a cognitive experiment.

Abstract: Provided is a hologram image normalization method for a holographic printer. In a holographic printing method according to an embodiment, generating, encoding, and normalizing for the (n+1)-th hogel are performed in parallel with loading and recording of a normalized hologram for the n-th hogel, and moving and waiting for the (n+1)-th hogel. Accordingly, a global maximum value and a global minimum value for normalization may be calculated as approximate estimation values, and a hologram generation process and a printing process may be performed in parallel, so that a total printing time may be minimized and memory usage may be optimized when holographic printing is performed.

Abstract: A vapor ablation handpiece for assisting a physician perform vapor ablation with a vapor ablation catheter includes a vapor generating element arranged in a coil shape. A mandrel seated in the body of the handpiece affixes the vapor generating element in the coiled arrangement. A voltage difference is supplied across the length of the vapor generating element when activated, causing the vapor generating element to heat liquid therein converting the liquid to vapor. The heated condensable vapor is delivered to a target tissue through the catheter.

Abstract: A vapor ablation handpiece for assisting a physician perform vapor ablation with a vapor ablation catheter includes a vapor generating element arranged in a coil shape. A mandrel seated in the body of the handpiece affixes the vapor generating element in the coiled arrangement. A voltage difference is supplied across the length of the vapor generating element when activated, causing the vapor generating element to heat liquid therein converting the liquid to vapor. The heated condensable vapor is delivered to a target tissue through the catheter.

Abstract: A vapor ablation handpiece for assisting a physician perform vapor ablation with a vapor ablation catheter includes a vapor generating element arranged in a coil shape. A mandrel seated in the body of the handpiece affixes the vapor generating element in the coiled arrangement. A voltage difference is supplied across the length of the vapor generating element when activated, causing the vapor generating element to heat liquid therein converting the liquid to vapor. The heated condensable vapor is delivered to a target tissue through the catheter.

Abstract: An apparatus for driving light-emitting diodes includes first and second light-emitting diode auxiliary drive parts for controlling the lighting of first and second light-emitting diode parts depending on the currents flowing through the first and second light-emitting diode parts, respectively detected by first and second resistors. Each of the first light-emitting diode auxiliary drive part and the second light-emitting diode auxiliary drive part includes a first transistor, a second transistor, and a third transistor.

Abstract: An apparatus for driving light-emitting diodes includes first and second light-emitting diode auxiliary drive parts for controlling the lighting of first and second light-emitting diode parts depending on the currents flowing through the first and second light-emitting diode parts, respectively detected by first and second resistors. Each of the first light-emitting diode auxiliary drive part and the second light-emitting diode auxiliary drive part includes a first transistor, a second transistor, and a third transistor.

Abstract: The present invention relates to a on silicon substrate, specifically to an inductor device and manufacturing method thereof for enhancing the quality factor of the inductor by disposing trenches on a silicon substratre, and by filling the inside of the trenches with polycrystalline polysilicon not doped with impurities. The present invention provides an inductor device and a manufacturing method thereof which can improve the quality factor by increasing resistance of the substrate by forming deep trenches disposed in specific patterns on a low-resistance silicon substrate and filling polycrystalline silicon not doped with impurities, and by reducing parasitic capacitance between the inductor and the silicon substrate.

Abstract: The present invention relates to a pillar bipolar transistor and the fabricating method thereof, the active region on which the emitter region, the base region and the collector region are formed, is defined at the first pillar by the trench formed in the semiconductor substrate, a party of the base region and the polysilicon base electrode is electrically connected by the base connection, thereby decreasing the contact area and protecting to increase the extrinsic region of the base, and protecting to mask a juction of base to emitter at high concentration. Also, the polysilicon emitter electrode having the wide surface area is formed by self-aligned contact using the CMP method on the upper of the emitter region.

Abstract: A bipolar transistor and a process for manufacturing thereof is disclosed. The bipolar transistor has a self-aligned base electrode in which first and second pillars are formed within first and second trenches which act as an activated region and a collector region, respectively; a conductive impurities layer of high density formed at a bottom side of the first and second trenches and at a lower portion of an isolation wall between the first and second trenches; and a sequentially formed base and emitter layer. After connection to the base layer, a base contact electrode is formed within the first trench, and a collector contact electrode is formed by implanting second conductive impurities in the second pillar.

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the s

Abstract: A dynamic random access memory (DRAM) with low noise characteristics comprises a plurality of memory cells each consisting of a pair of reference memory cells respectively arranged between a word line and a pair of adjacent bit lines. The reference memory cells store signals of opposite levels corresponding to one bit of information. Each of the reference memory cells consists of a capacitor and switching transistor. One end of the capacitor is connected to the collector of the transistor. The other end of the capacitor is connected to one of the pair of bit lines adjacent thereto. The base of the transistor is connected to the word line, and the emitter of the transistor is completed to receive a reference voltage.

Abstract: A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Abstract: A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.