Abstract: An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage.

Abstract: An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage.

Abstract: An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage.

Abstract: An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage.

Abstract: A power converter includes a power converting unit and a driving circuit. The power converting unit generates a DC output voltage based on a pull up driving signal, a pull down driving signal, and a DC input voltage. The driving circuit compensates for an inductor peak current, and performs in a pulse-frequency-modulation (PFM) mode and a pulse-width-modulation (PWM) mode to generate the pull-up driving signal and the pull-down driving signal based on the DC output voltage and the compensated inductor peak current. The power converter performs a mode transition between the PFM and PWM modes at a uniform load current, even when a magnitude of the DC output voltage varies.

Abstract: A power converter includes a zero-current detector having an adjustable offset voltage. The power converter includes a power converting unit and a switch driving circuit. The power converting unit generates a DC output voltage based on a pull-up driving signal, a pull-down driving signal and a DC input voltage. The switch driving circuit generates a first detection voltage signal based on the DC output voltage. The switch driving circuit includes a zero-current detector configured to adjust an offset voltage based on the first detection voltage signal and generate a zero-current detecting signal based on the offset voltage. The offset voltage and the zero-current detecting signal are associated with a current in the power converting unit. The switch driving circuit also includes a pulse-frequency modulating circuit configured to perform a pulse-frequency modulation (PFM) to generate the pull-up driving signal and the pull-down driving signal based on the zero-current detecting signal.

Abstract: A voltage biasing circuit includes a metal-oxide-semiconductor (MOS) transistor, a voltage control circuit controlling a voltage between a gate and a source of the MOS transistor to operate the MOS transistor in a sub-threshold range, and a capacitor connected to the MOS transistor. The voltage biasing circuit may further include a voltage buffer connected between the voltage control circuit and the MOS transistor.

Abstract: A power converter includes a power converting unit and a driving circuit. The power converting unit generates a DC output voltage based on a pull up driving signal, a pull down driving signal, and a DC input voltage. The driving circuit compensates for an inductor peak current, and performs in a pulse-frequency-modulation (PFM) mode and a pulse-width-modulation (PWM) mode to generate the pull-up driving signal and the pull-down driving signal based on the DC output voltage and the compensated inductor peak current. The power converter performs a mode transition between the PFM and PWM modes at a uniform load current, even when a magnitude of the DC output voltage varies.

Abstract: A power converter includes a zero-current detector having an adjustable offset voltage. The power converter includes a power converting unit and a switch driving circuit. The power converting unit generates a DC output voltage based on a pull-up driving signal, a pull-down driving signal and a DC input voltage. The switch driving circuit generates a first detection voltage signal based on the DC output voltage. The switch driving circuit includes a zero-current detector configured to adjust an offset voltage based on the first detection voltage signal and generate a zero-current detecting signal based on the offset voltage. The offset voltage and the zero-current detecting signal are associated with a current in the power converting unit.

Abstract: A voltage biasing circuit includes a metal-oxide-semiconductor (MOS) transistor, a voltage control circuit controlling a voltage between a gate and a source of the MOS transistor to operate the MOS transistor in a sub-threshold range, and a capacitor connected to the MOS transistor. The voltage biasing circuit may further include a voltage buffer connected between the voltage control circuit and the MOS transistor.

Abstract: A voltage-controlled oscillator (VCO) for a multi-band receiver, and a radio-frequency (RF) communication apparatus having the same. The VCO includes at least two fine tune branches, that is, a main fine tune branch and an auxiliary fine tune branch. The main fine tune branch includes at least one variable capacitor whose capacitance varies according to a tuning voltage. The auxiliary fine tune branch includes at least one varactor that operates either as a variable capacitor whose capacitance varies according to the tuning voltage or a fixed capacitor regardless of the tuning voltage, based on an operating frequency band. Accordingly, it is possible to prevent phase noise from increasing by varying the gain of the VCO according to the frequency band of an oscillation signal from the VCO.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A frequency fine tuning circuit for use in a voltage-controlled oscillator is provided. The frequency tuning circuit includes a first varactor, a second varactor and a center bias unit. The second varactor is coupled to the first varactor at a first node. The center bias unit maintains a node voltage of the first node at a constant bias voltage level.

Abstract: A voltage controlled oscillator includes an L-C tank circuit configured to have a first capacitance that increases as a power supply voltage increases, and a capacitance compensation circuit configured to be connected in parallel with both terminals of the L-C tank circuit and to have a second capacitance that decreases as the power supply voltage increases. The voltage controlled oscillator maintains the sum of the first capacitance and the second capacitance constant regardless of the fluctuation of the power supply voltage, thereby maintaining a stable oscillation frequency.

Abstract: A voltage-controlled oscillator (VCO) for a multi-band receiver, and a radio-frequency (RF) communication apparatus having the same. The VCO includes at least two fine tune branches, that is, a main fine tune branch and an auxiliary fine tune branch. The main fine tune branch includes at least one variable capacitor whose capacitance varies according to a tuning voltage. The auxiliary fine tune branch includes at least one varactor that operates either as a variable capacitor whose capacitance varies according to the tuning voltage or a fixed capacitor regardless of the tuning voltage, based on an operating frequency band. Accordingly, it is possible to prevent phase noise from increasing by varying the gain of the VCO according to the frequency band of an oscillation signal from the VCO.

Abstract: For use in a multi-band wireless communication system, a local oscillator includes a voltage-controlled oscillator that generates an oscillating signal in response to a control signal. A local oscillating signal generator includes buffers and frequency dividers for generating from the oscillating signal a plurality of frequency signals having different frequencies. A switching circuit selects one of the frequency signals, and a phase locked loop generates the control signal from the selected frequency signal.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A frequency fine tuning circuit for use in a voltage-controlled oscillator is provided. The frequency tuning circuit includes a first varactor, a second varactor and a center bias unit. The second varactor is coupled to the first varactor at a first node. The center bias unit maintains a node voltage of the first node at a constant bias voltage level.

Abstract: For use in a multi-band wireless communication system, a local oscillator includes a voltage-controlled oscillator that generates an oscillating signal in response to a control signal. A local oscillating signal generator includes buffers and frequency dividers for generating from the oscillating signal a plurality of frequency signals having different frequencies. A switching circuit selects one of the frequency signals, and a phase locked loop generates the control signal from the selected frequency signal.