Patents by Inventor Jin-Hyung Cho
Jin-Hyung Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138260Abstract: The present disclosure relates to a plurality of host materials, an organic electroluminescent compound, and an organic electroluminescent device comprising the same. By comprising a specific combination of host compounds and/or an organic electroluminescent compound according to the present disclosure as an organic electroluminescent material, an organic electroluminescent device having low driving voltage and/or high luminous efficiency and/or long lifespan characteristics can be provided.Type: ApplicationFiled: September 8, 2023Publication date: April 25, 2024Inventors: Ji-Song JUN, Hong-Se OH, Dong-Hyung LEE, Sang-Hee CHO, Du-Yong PARK, Hyun-Woo KANG, Jin-Man KIM
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Patent number: 11963439Abstract: The present disclosure relates to an organic electroluminescent compound and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure, it is possible to produce an organic electroluminescent device having improved driving voltage, power efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.Type: GrantFiled: August 24, 2022Date of Patent: April 16, 2024Assignee: Rohm and Haas Electronic Materials Korea Ltd.Inventors: Eun-Joung Choi, Young-Kwang Kim, Su-Hyun Lee, So-Young Jung, YeJin Jeon, Hong-Se Oh, Dong-Hyung Lee, Jin-Man Kim, Hyun-Woo Kang, Mi-Ja Lee, Hee-Ryong Kang, Hyo-Nim Shin, Jeong-Hwan Jeon, Sang-Hee Cho
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Patent number: 11961775Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: November 8, 2022Date of Patent: April 16, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Publication number: 20240104990Abstract: Disclosed herein is a method for user-centered visitor access management, which may include issuing, by a management office server, a digital certificate to a householder terminal; registering, by a wall-pad, a householder in response to a request to register the householder based on the digital certificate; requesting, by the householder terminal, the management office server to register a visitor based on a visit request from a visitor terminal and delegating the digital certificate to the visitor terminal; making an entry request to a management terminal based on the digital certificate; verifying, by the wall-pad, the digital certificate based on a request for verification for entry from a wall-pad management terminal and providing a verification result to the wall-pad management terminal when the management terminal is the wall-pad management terminal; and managing and controlling, by the wall-pad, permission to use home devices based on delegated permission information of the digital certificate.Type: ApplicationFiled: March 22, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Hyun KIM, Young-Seob CHO, Soo-Hyung KIM, Geon-Woo KIM, Young-Sam KIM, Jong-Hyouk NOH, Kwan-Tae CHO, Sang-Rae CHO, Jin-Man CHO, Seung-Hun JIN
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Publication number: 20240104115Abstract: Disclosed herein are a method and apparatus for converting a credential data schema.Type: ApplicationFiled: July 11, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Hyun KIM, Soo-Hyung KIM, Young-Seob CHO, Geon-Woo KIM, Young-Sam KIM, Jong-Hyouk NOH, Kwan-Tae CHO, Sang-Rae CHO, Jin-Man CHO, Seung-Hun JIN
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Publication number: 20230389474Abstract: An annotation method for acquiring a training data set for training a ripeness determination model for target fruits is provided. The annotation method includes the steps of: acquiring at least one image; extracting a characteristic area for the target fruits included in the at least one image; calculating a first parameter for a first color and a second parameter for a second color on the basis of a pixel value included in the characteristic area; and acquiring labeling data for the characteristic area on the basis of at least the first parameter and the second parameter.Type: ApplicationFiled: August 24, 2023Publication date: December 7, 2023Applicant: AGRICULTURAL CORPORATION IOCROPS INC.Inventor: Jin Hyung CHO
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Patent number: 10599383Abstract: A method for operating an electronic device is provided, including: obtaining music information associated with music that is being played by the electronic device; and outputting a visual effect through a display of the electronic device based on the music information. According to another aspect of the disclosure, an electronic device is provided including a display and a processor configured to: obtain music information associated with music that is being played by the electronic device; and output a visual effect through the display based on the music information.Type: GrantFiled: June 19, 2015Date of Patent: March 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-Ree Na, Ji-Hee Yoon, Jin-Hyung Cho, Ja-Kyoung Lee, Hye-Eun Lee
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Publication number: 20160035323Abstract: A method for operating an electronic device is provided, including: obtaining music information associated with music that is being played by the electronic device; and outputting a visual effect through a display of the electronic device based on the music information. According to another aspect of the disclosure, an electronic device is provided including a display and a processor configured to: obtain music information associated with music that is being played by the electronic device; and output a visual effect through the display based on the music information.Type: ApplicationFiled: June 19, 2015Publication date: February 4, 2016Inventors: Hae-Ree NA, Ji-Hee YOON, Jin-Hyung CHO, Ja-Kyoung LEE, Hye-Eun LEE
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Patent number: 8129745Abstract: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external enviroType: GrantFiled: April 3, 2009Date of Patent: March 6, 2012Assignee: Nextron CorporationInventors: Hak Beom Moon, Jin Hyung Cho, Suc Hyun Bang, Cheol Hwan Kim, Yoon Hyung Jang
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Patent number: 7996050Abstract: An input device for an electronic device is provided that includes a base, a frame pivotally connected to the base, a roller member rotatably supported by the frame, and at least one button pivotally connected at a side of the base. An electronic device is also provided that includes a first body, a second body pivotally attached to the first body, and an input device located in the first body.Type: GrantFiled: February 28, 2007Date of Patent: August 9, 2011Assignee: LG Electronics Inc.Inventors: Chang-Bai Won, Jin-Hyung Cho, June-Wook Jeong
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Publication number: 20110133854Abstract: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external enviroType: ApplicationFiled: April 3, 2009Publication date: June 9, 2011Inventors: Hak Beom Moon, Jin Hyung Cho, Suc Hyun Bang, Cheol Hwan Kim, Yoon Hyung Jang
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Patent number: 7868648Abstract: An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.Type: GrantFiled: February 27, 2008Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-jin Lee, Jin-hyung Cho
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Patent number: 7480196Abstract: A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.Type: GrantFiled: January 11, 2007Date of Patent: January 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyung Cho, Hi-Choon Lee
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Patent number: 7436730Abstract: In an embodiment, a device controls an internal power voltage in a semiconductor device. The device uses internal and external power voltages during a power-up period, and includes a power-up flag signal generator and a control circuit. The power-up flag signal generator generates a power-up flag signal based on the external power voltage. The control circuit provides a first internal power voltage to a peripheral circuit of the semiconductor device. During power-up the first internal power voltage varies according to a level of the external power voltage in response to the power-up flag signal having a first logic level. Accordingly, an internal power voltage may have a linear power-up slope during the power-up period and an initialization failure of any latch circuits in the peripheral circuit may be avoided. Also, power consumption of the latch circuits is reduced.Type: GrantFiled: June 15, 2005Date of Patent: October 14, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Jin-Hyung Cho
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Publication number: 20080204071Abstract: An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.Type: ApplicationFiled: February 27, 2008Publication date: August 28, 2008Inventors: Dong-jin Lee, Jin-hyung Cho
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Publication number: 20070210828Abstract: An input device for an electronic device is provided that includes a base, a frame pivotally connected to the base, a roller member rotatably supported by the frame, and at least one button pivotally connected at a side of the base. An electronic device is also provided that includes a first body, a second body pivotally attached to the first body, and an input device located in the first body.Type: ApplicationFiled: February 28, 2007Publication date: September 13, 2007Applicant: LG Electronics Inc.Inventors: Chang-Bai Won, Jin-Hyung Cho, June-Wook Jeong
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Patent number: 7248517Abstract: Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.Type: GrantFiled: May 14, 2005Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hi-Choon Lee, Jin-Hyung Cho
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Publication number: 20070165470Abstract: A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.Type: ApplicationFiled: January 11, 2007Publication date: July 19, 2007Inventors: Jin-Hyung Cho, Hi-Choon Lee
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Publication number: 20060120182Abstract: Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.Type: ApplicationFiled: May 14, 2005Publication date: June 8, 2006Applicant: Samsung Electronics Co., LTD.Inventors: Hi-Choon Lee, Jin-Hyung Cho
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Publication number: 20050275986Abstract: In an embodiment, a device controls an internal power voltage in a semiconductor device. The device uses internal and external power voltages during a power-up period, and includes a power-up flag signal generator and a control circuit. The power-up flag signal generator generates a power-up flag signal based on the external power voltage. The control circuit provides a first internal power voltage to a peripheral circuit of the semiconductor device. During power-up the first internal power voltage varies according to a level of the external power voltage in response to the power-up flag signal having a first logic level. Accordingly, an internal power voltage may have a linear power-up slope during the power-up period and an initialization failure of any latch circuits in the peripheral circuit may be avoided. Also, power consumption of the latch circuits is reduced.Type: ApplicationFiled: June 15, 2005Publication date: December 15, 2005Inventor: Jin-Hyung Cho