Patents by Inventor Jin-Il Hyun

Jin-Il Hyun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5737362
    Abstract: The present invention provides a double delay-locked loop(DDLL) code tracking loop for spreading a linear section of an energy detecting area of the tracking loop by using several code time, and provides a delay-locked loop code tracking system for a receiver of a code spread communication system capable of performing an effective code tracking even when a changing ratio of a receiving path is large, by variably using a difference of a preceding time code and a delayed time code according to a change of a receiving environment being changed without cease. Accordingly, the code tracking loop of the present invention improves the receiver performance of the code spread radio communication system, and simplifies a structure of the receiver.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: April 7, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jin-Il Hyun, In Kang, Jin-Jong Cha, Jae-Seok Kim, Kyung-Soo Kim
  • Patent number: 5726925
    Abstract: A Hadamard transformer is disclosed which uses memory cells in a digital signal processor for restoring to the original signals at a receiving end from the signals which have been transformed to a Hadamard function sequenced at a transmitting end. The Hadamard transformer using memory cells includes a counter which receives sample data clocks to output counted signals to a memory address generator and to a plurality of adder/subtractors. The plurality of adder/subtractors add and subtract the input signals and the data read from a memory in accordance with the counted signals of the counter so as to write or record the results into the memory. The memory address generator generates memory addresses in accordance with the sample data clock and the counted signals so that the memory can be read and written to. The memory thus stores the data inputted and outputted to and from the plurality of sadder/subtractors in accordance with the memory addresses generated by the memory address generator.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: March 10, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jin-Il Hyun, Jin-Jong Cha, In Kang