Patents by Inventor Jin Il Oh

Jin Il Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127094
    Abstract: Disclosed herein are a logical qubit execution apparatus and method. The logical qubit execution apparatus may be configured to execute, by a logical execution layer, a quantum circuit including requested logical qubits using a lattice surgery operation, generate, by the logical execution layer, measurement results of the logical qubits by combining measurement results of logical Pauli frames, generate, by a physical execution layer, a physical qubit circuit by converting a logical qubit operation corresponding to the measurement results of the logical qubits into a physical qubit operation, and measure, by the physical execution layer, results of an operation on physical Pauli frames by executing the physical qubit circuit.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 18, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho ON, Chei-Yol KIM, Soo-Cheol OH, Sang-Min LEE, Gyu-Il CHA
  • Patent number: 11949881
    Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 2, 2024
    Assignees: Electronics and Telecommunications Research Institute, Kwangwoon University Research Institute for Industry Cooperation, Industry-Academia Cooperation Group of Sejong University
    Inventors: Se-Yoon Jeong, Hae-Chul Choi, Jeong-Il Seo, Seung-Kwon Beack, In-Seon Jang, Jae-Gon Kim, Kyung-Ae Moon, Dae-Young Jang, Jin-Woo Hong, Jin-Woong Kim, Yung-Lyul Lee, Dong-Gyu Sim, Seoung-Jun Oh, Chang-Beom Ahn, Dae-Yeon Kim, Dong-Kyun Kim
  • Patent number: 9589964
    Abstract: A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhyun Lim, Hyun-Chul Yoon, Younghan Kim, Jin Il Oh, Soonwon Hwang