Abstract: A light emitting diode is provided. The light emitting diode includes: a n-type semiconductor layer; a p-type semiconductor layer facing the n-type semiconductor layer; an active layer formed between the n-type semiconductor layer and the p-type semiconductor layer; and a nanopattern metal layer that is formed in a predetermined pattern on a surface of one of the n-type semiconductor layer and the p-type semiconductor layer, from which light is generated by the active layer, and changes a light path to improve the light extraction efficiency. Thus the light extraction efficiency of the light emitting diode is improved.

Abstract: An apparatus and method for recording/playing a moving picture in a digital broadcast receiver is disclosed, which supports a trick mode. If digital broadcasting is recorded, the digital broadcasting is converted into a video sequence having a new format and frame type, such as an I frame structure, and then recorded in a recording medium. Also, corresponding I frame is directly uploaded and played in accordance with times speed of trick play using the frame index of video data recorded after being converted into the I frame. Thus, it is possible to normally provide more elaborate moving picture trick play for every times speed.

Abstract: The present invention provides an apparatus and method for decoding a video clip image as well as a moving picture of a specific channel compressed by MPEG using a video decoder. Specifically, the present invention restores video clip data such as a data broadcast intra frame still picture, a video drip, and the like using the video decoder to output the restored data to a screen, thereby reducing the load and memory access of the host processor. And, the present invention decodes animation OSD data via the video decoder to output to the screen, thereby implementing high quality OSD with an inexpensive cost.

Abstract: A dual video decoder of a digital broadcasting receiver is provided. The decoder includes: a first PES decoder for decoding a first video PES outputted from a first system decoder, into a first video ES; a second PES decoder for decoding a second video PES outputted from a second system decoder, into a second video ES; a VBV (Video Buffer Verifier) buffer memory divided into a first video ES region and a second video ES region; a decoding controller for outputting a control signal to determine a to-be-decoded video ES among the first and second video ESs, and independently decode the first and second video ESs in a single decoding unit; and the single decoding unit for reading the to-be-decoded video ES from the corresponding region of the VBV buffer memory.

Abstract: An apparatus and method for processing video signals, which can selectively freeze any one of two or more images being displayed, are disclosed. The apparatus includes a video decoder decoding at least one video stream in picture units, by using a plurality of decoding frames and at least one freezing frame, a memory storing in picture units the decoded video stream outputted from the video decoder, and a plurality of video processors reading the stored video stream from the memory and transforming the stored video stream to displayable data.