Abstract: In the present invention, a reference block data within a current image from which a motion vector will be obtained and corresponding search region data within reproduced previous image are stored in a reference block and a search region data memory, respectively. A motion vector of two pixels unit is performed using the reference block and the search region data stored in the memory, thus resulting in obtained a motion vector of two pixels unit. At this time, the reference block and the search region data are used by performing 2:1 sampling in a horizontal direction and a vertical direction, respectively and the search range is ?7˜+7. The structure of the motion search is consisted of a memory for storing a reference block (8×8) of current images and a memory (24×8) for storing a search region storing reproduced previous images.

Abstract: An apparatus for motion estimation with control part implemented by state transition diagram without adding delay circuits to processing elements, and capable of maintaining a regular data flow and easily implementing hardware to improve a power consume and speed is disclosed. The apparatus comprises a first and second storage parts for storing data; a measurement part for finding an absolute difference between the data; a step decision part for determining a minimum value; and a control part implemented by state transition diagram.

Abstract: In the present invention, a reference block data within a current image from which a motion vector will be obtained and corresponding search region data within reproduced previous image are stored in a reference block and a search region data memory, respectively. A motion vector of two pixels unit is performed using the reference block and the search region data stored in the memory, thus resulting in obtained a motion vector of two pixels unit. At this time, the reference block and the search region data are used by performing 2:1 sampling in a horizontal direction and a vertical direction, respectively and the search range is −7˜+7. The structure of the motion search is consisted of a memory for storing a reference block (8×8) of current images and a memory (24×8) for storing a search region storing reproduced previous images.

Abstract: An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, includes a first storage device for temporarily storing the run representing the number of zeros (‘0’s) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulatin

Abstract: A video data run length decoding apparatus is disclosed.

Abstract: The present invention provides a double delay-locked loop(DDLL) code tracking loop for spreading a linear section of an energy detecting area of the tracking loop by using several code time, and provides a delay-locked loop code tracking system for a receiver of a code spread communication system capable of performing an effective code tracking even when a changing ratio of a receiving path is large, by variably using a difference of a preceding time code and a delayed time code according to a change of a receiving environment being changed without cease. Accordingly, the code tracking loop of the present invention improves the receiver performance of the code spread radio communication system, and simplifies a structure of the receiver.

Abstract: A Hadamard transformer is disclosed which uses memory cells in a digital signal processor for restoring to the original signals at a receiving end from the signals which have been transformed to a Hadamard function sequenced at a transmitting end. The Hadamard transformer using memory cells includes a counter which receives sample data clocks to output counted signals to a memory address generator and to a plurality of adder/subtractors. The plurality of adder/subtractors add and subtract the input signals and the data read from a memory in accordance with the counted signals of the counter so as to write or record the results into the memory. The memory address generator generates memory addresses in accordance with the sample data clock and the counted signals so that the memory can be read and written to. The memory thus stores the data inputted and outputted to and from the plurality of sadder/subtractors in accordance with the memory addresses generated by the memory address generator.