Abstract: A memory device includes a bit line, a first word line, a bit line contact, an electrode, a second word line and a contact tip. The bit line may extend along a first direction. The first word line is formed over the bit line and extends in a second direction. The bit line contact is formed between adjacent first word lines. The bit line contact may have an upper face substantially higher than the first word lines. The electrode contacting with the bit line contact may include an elastic material bending by an electric field among the electrode, the first word line and the second word line. The second word line is disposed over the electrode and corresponds to at least one of the first word lines. The contact tip formed at a lateral portion of the electrode may protrude toward the first and the second word lines.

Abstract: Example embodiments relate to a memory card including a generally box-shaped printed circuit board, a control chip in the generally box-shaped printed circuit board, a memory chip in the generally box-shaped printed circuit board, and a plurality of contact pads on at least two portions of an upper portion, a lower portion, a left portion and a right portion of a front face of the generally box-shaped printed circuit board, and on at least two portions of an upper portion, a lower portion, a left portion and a right portion of a rear face of the generally box-shaped printed circuit board.

Abstract: A memory device includes a bit line, a reading word line, a bit line contact, an electrode, a writing word line and a contact tip. The bit line is formed on a substrate. The reading word line is formed over the bit line. The bit line contact is disposed between adjacent reading word lines. The electrode extends substantially in parallel to the reading word line and includes a conductive material being bent in response to an applied voltage. The writing word line is formed over the electrode and is separated from the electrode. The contact tip is formed at an end portion of the electrode and is separated from the reading and the writing word lines. The contact tip protrudes toward the reading word line or writing word line.

Abstract: An overlay measuring apparatus includes a light source which generates visible light with a plurality of wavelengths, an optical module which selects visible light with a single wavelength from the visible light generated by the light source, makes the visible light with a single wavelength incident on a plurality of overlay patterns, and uses visible light reflected from the plurality of overlay patterns to project the overlay patterns with a predetermined color, an imaging unit which acquires images of the plurality of overlay patterns according to individual wavelengths of the visible light and acquires corresponding image signals, and a control unit which outputs a control signal to the optical module so that the optical module can project the overlay pattern with a specific color using information associated with the individual wavelengths of the visible light that is used to project the overlay pattern image selected by a selection unit.

Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

Abstract: Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate.

Abstract: In a photoresist dispensing apparatus for use in manufacturing a semiconductor device, to coercively emit photoresist from a bottle by using a dispensing pump and to pass it through a supply line and a filter to obtain a filtering operation, and to spray the filtered photoresist to a wafer through a spraying nozzle; a bubble removal unit is equipped with the supply line, before the dispensing pump. Large and micro bubbles generated in the midst of flow of photoresist, and foreign substances, are substantially filtered off so as to supply photoresist of a good quality. A floating load in a foreign substance removal filter is substantially removed, thus spraying photoresist under an always uniform and stabilized pressure by using a dispensing pump, to cover a wafer with photoresist in a uniform thickness and obtain a precise pattern formation.

Abstract: A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension; and a bit line insulated from the plurality of word lines, intersecting the plurality of word lines and extending in a second direction of extension, a transition electrode portion of the bit line positioned in the gap and spaced apart from the plurality of word lines by a predetermined distance, the transition electrode portion of the bit line configured and arranged to be bent toward any one of the plurality of word lines in response to an electrical signal applied to at least one of the plurality of word lines.

Abstract: Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate, at opposite ends of the pre-active pattern. The interchannel layers are then selectively removed, to form tunnels passing through the pre-active pattern, thereby defining an active channel pattern including the tunnels and channels including the channel layers. The channels are doped with phosphorus after selectively removing the interchannel layers. A gate electrode is then formed in the tunnels and surrounding the channels.

Abstract: A photo-resist dispensing apparatus is disclosed and comprises; a tank adapted to hold a photo-resist solution, a pump unit adapted to pump the photo-resist solution from the tank, a filter unit adapted to receive the photo-resist solution from the pump unit, and at least one of a first gas discharge unit connected to the tank and adapted to remove gas bubbles from the photo-resist solution held in the tank, and a second gas discharge unit connected to the filter unit and adapted to remove gas bubbles from the photo-resist solution in the filter.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: An apparatus for catching byproducts in semiconductor device processing equipment is disposed in an exhaust line between a process chamber and a vacuum pump. The apparatus includes a cylindrical trap housing member, an upper cover and a lower cover covering the upper part and lower part of the trap housing, respectively, a heater disposed under the upper cover, first and second cooling plates disposed in the trap housing, a post spacing the cooling plates, apart and a cooling system for cooling respective portions of the apparatus. The cooling system includes a delivery pipe for supplying refrigerant, a discharge pipe for discharging the refrigerant from the apparatus, first cooling piping extending through each cooling plate and connected to the delivery and discharge pipes, and second cooling piping extending helically along the outer circumferential surface of the trap housing.

Abstract: An apparatus traps residual products before the products can be formed in or flow to a vacuum pump in semiconductor device manufacturing equipment. The apparatus is connected between a process chamber and the vacuum pump and includes first and second cooling plates alternately disposed inside a hollow cylindrical housing. The first cooling plates each have a base and a grid projecting from a surface of the base, and define a vent hole extending through a central portion of the base. Each of the second cooling plates have a base and a grid projecting from a surface of the base, and define a plurality of vent holes extending through an outer peripheral portion of the base. Gaseous products flowing from a process chamber and through the housing are transformed into powder that adheres to the cooling plates.

Abstract: Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate.

Abstract: A memory card includes a printed circuit board (PCB) defining an interior space. A control chip is in the interior space. A memory chip is electrically coupled to the control chip. A contact pad is on the PCB outside the interior space. A converting member is located outside the interior space. The converting member is configured to provide an indication to the control chip to change an application function of the control chip and an interface function of the contact pad based on an external input to the memory card. A multi-interface member is located completely inside the interior space of the PCB and electrically coupled to the control chip and the converting member to change the application function of the control chip and the interface function of the contact pad based on operations of the converting member.

Abstract: A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on an inner surface of the gate recess, forming a first silicon layer on the semiconductor substrate including the gate insulation layer to form an open void within the gate recess, forming a stop layer having a high thermal resistance on the first silicon layer to prevent a void from moving around within the gate recess, forming a second silicon layer on the first silicon layer, and patterning the second and the first silicon layers to form a gate electrode.

Abstract: A memory device includes a bit line, a reading word line, a bit line contact, an electrode, a writing word line and a contact tip. The bit line is formed on a substrate. The reading word line is formed over the bit line. The bit line contact is disposed between adjacent reading word lines. The electrode extends substantially in parallel to the reading word line and includes a conductive material being bent in response to an applied voltage. The writing word line is formed over the electrode and is separated from the electrode. The contact tip is formed at an end portion of the electrode and is separated from the reading and the writing word lines. The contact tip protrudes toward the reading word line or writing word line.

Abstract: A memory device includes a bit line, a first word line, a bit line contact, an electrode, a second word line and a contact tip. The bit line may extend along a first direction. The first word line is formed over the bit line and extends in a second direction. The bit line contact is formed between adjacent first word lines. The bit line contact may have an upper face substantially higher than the first word lines. The electrode contacting with the bit line contact may include an elastic material bending by an electric field among the electrode, the first word line and the second word line. The second word line is disposed over the electrode and corresponds to at least one of the first word lines. The contact tip formed at a lateral portion of the electrode may protrude toward the first and the second word lines.

Abstract: A complex memory chip includes a peripheral circuit block, a memory block for storing data, and a control block for controlling functions of the peripheral circuit block and the memory block. The peripheral circuit block, the memory block and the control block are formed as a single chip. Further, a memory card includes a printed circuit board, the complex memory chip formed on a first face of the printed circuit board, a wire for electrically connecting the complex memory chip to the printed circuit board, a contact pad formed on a second face of the printed circuit board opposite to the first face to be electrically connected to the complex memory chip, and a molding member for fixing the complex memory chip to the printed circuit board.

Abstract: There are provided a memory device capable of writing and reading data at a low voltage and a method of manufacturing the same. The memory device comprises: a bit line formed in one direction; a plurality of word lines provided crosswise above the bit line, the word lines formed in parallel with a vacant space formed therebetween; a flip electrode electrically connected to the bit line, formed over one of the word lines above the bit line to pass the vacant space, and configured to be bent in one direction with respect to the plurality of word lines by electric fields induced between the plurality of word lines; and a contact part protruding from a lower end of the flip electrode concentrates charges induced by the flip electrode in response to charges applied by the word line to selectively bring the word line into contact with the flip electrode.