Patents by Inventor Jin-Kee Choi

Jin-Kee Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970732
    Abstract: The present invention relates to a method for determining the DNA quality of a biological sample and, more specifically, to a method for determining the DNA quality of a biological sample by performing a quantitative polymerase chain reaction (PCR) using primers capable of amplifying a target gene, a method for preparing the primers used in the method, and a method for standardizing the amount of detected target gene mutation by using the determined DNA quality. The method of the present invention enables objective evaluation of the DNA quality of a biological sample used in gene analysis and the presentation of objective results on the expression ratio of a gene mutation, thereby providing reliable information in the fields of clinical research and companion diagnosis.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 30, 2024
    Assignees: GENCURIX INC., LOGONE BIO CONVERGENCE RESEARCH FOUNDATION
    Inventors: Young Kee Shin, Jin Ju Kim, Sung Su Kim, Hyun Jeung Choi, Young Ho Moon, Myung Sun Kim, Jee Eun Kim
  • Patent number: 7148116
    Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 12, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
  • Patent number: 7084478
    Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
  • Publication number: 20050255662
    Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 17, 2005
    Inventors: Won Lee, Joon-Mo Kwon, Tae Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
  • Publication number: 20030178697
    Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
    Type: Application
    Filed: October 16, 2002
    Publication date: September 25, 2003
    Inventors: Won Shik Lee, Joon-Mo Kwon, Tae Kyung Kim, Jin-Kee Choi, Dong-Gun Park, Hyeong-Chan Ko, Hong-Joon Moon
  • Patent number: 6339251
    Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: January 15, 2002
    Assignee: Samsung Electronics Co., LTD
    Inventors: Min-Seok Ha, Jin-Kee Choi, Cheol Jeong
  • Publication number: 20010014515
    Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.
    Type: Application
    Filed: November 29, 1999
    Publication date: August 16, 2001
    Inventors: MIN-SEOK HA, JIN-KEE CHOI, CHEOL JEONG
  • Patent number: 6025250
    Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: February 15, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Seok Ha, Jin-Kee Choi, Cheol Jeong