Patents by Inventor Jin Ki Kim
Jin Ki Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200357477Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.Type: ApplicationFiled: May 29, 2020Publication date: November 12, 2020Inventors: Jin-Ki KIM, Peter B. GILLINGHAM
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Publication number: 20200258971Abstract: A display device includes a display substrate, a main circuit board, and first and second connection circuit boards. The display substrate includes a base layer, an insulating layer on the base layer, a first signal line on the base layer, a second signal line on the base layer, a first pad exposed from the insulating layer and connected to the first signal line, and a second pad connected to a side surface of the second signal line and disposed on a side surface and a bottom surface of the base layer. The first connection circuit board electrically connects the first pad and the main circuit board, and the second connection circuit board electrically connects the second pad and the main circuit board.Type: ApplicationFiled: February 5, 2020Publication date: August 13, 2020Inventors: Joonho OH, Seungjae KANG, Myung-Seok KWON, Yun-Tae KIM, Jin-Ki KIM, Hasook KIM
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Patent number: 10706943Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.Type: GrantFiled: December 17, 2018Date of Patent: July 7, 2020Assignee: Conversant Intellectual Property Management Inc.Inventors: Jin-Ki Kim, Peter B. Gillingham
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Patent number: 10705736Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.Type: GrantFiled: April 18, 2019Date of Patent: July 7, 2020Inventor: Jin-Ki Kim
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Patent number: 10679695Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: January 16, 2019Date of Patent: June 9, 2020Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20190303004Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.Type: ApplicationFiled: April 18, 2019Publication date: October 3, 2019Inventor: Jin-Ki KIM
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Publication number: 20190214077Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: January 16, 2019Publication date: July 11, 2019Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Publication number: 20190189225Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.Type: ApplicationFiled: December 17, 2018Publication date: June 20, 2019Inventors: Jin-Ki KIM, Peter B. GILLINGHAM
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Patent number: 10303370Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.Type: GrantFiled: May 10, 2018Date of Patent: May 28, 2019Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.Inventor: Jin-Ki Kim
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Patent number: 10236032Abstract: A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.Type: GrantFiled: September 18, 2008Date of Patent: March 19, 2019Assignee: Novachips Canada Inc.Inventors: HakJune Oh, Jin-Ki Kim
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Patent number: 10223003Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.Type: GrantFiled: November 9, 2017Date of Patent: March 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: Jin-Ki Kim, Hong Beom Pyeon
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Patent number: 10224098Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: March 28, 2018Date of Patent: March 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Patent number: 10199113Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.Type: GrantFiled: May 17, 2017Date of Patent: February 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: Jin-Ki Kim, Peter B. Gillingham
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Publication number: 20180329627Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.Type: ApplicationFiled: May 10, 2018Publication date: November 15, 2018Inventor: Jin-Ki KIM
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Publication number: 20180261282Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: March 28, 2018Publication date: September 13, 2018Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 10007439Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.Type: GrantFiled: January 6, 2017Date of Patent: June 26, 2018Assignee: Conversant Intellectual Property Management Inc.Inventor: Jin-Ki Kim
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Patent number: 9996274Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.Type: GrantFiled: January 30, 2017Date of Patent: June 12, 2018Assignee: Conversant Intellectual Property Management Inc.Inventor: Jin-Ki Kim
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Patent number: 9977731Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.Type: GrantFiled: September 16, 2013Date of Patent: May 22, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: Hong Beom Pyeon, Jin-Ki Kim, Peter B. Gillingham
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Publication number: 20180137912Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 9972381Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: January 11, 2018Date of Patent: May 15, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim