Abstract: A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control signal so as to control a supply of the first or second voltage to the MOS logic; and a fuse unit disposed between the supply terminal of the first voltage or the second voltage and the switching transistor unit, for cutting off a supply of the first or second voltage to the switching transistor unit by a selective cut based on a test result. Whereby, a product development or production difficulty or a yield decrease based on a performance drop or leakage current increase in a circuit having a power gate or MTCMOS may be improved. In addition, a product development delay caused by a mask revision required at a transistor level may be improved in a revision of an NMOS or PMOS transistor.

Abstract: A multichip and method of testing a multichip, the multichip including a control chip having a central processing unit (CPU) and a plurality of memories, each memory of the plurality of memories storing information related to testing the multichip, comprises connecting one of the memories to the control chip; reading, by the CPU, stored memory information from the connected one of the memories to confirm the connected one of the memories; generating a test pattern relating to the connected one of the memories confirmed by the CPU, and testing the connected one of the memories according to the test pattern.

Abstract: Marking lines or patterns are formed among dummy patterns or on a reference plain of a semiconductor device requiring analysis to enable easy location of a point on the semiconductor device.

Abstract: A pipeline test apparatus is provided. The pipeline test apparatus includes a test board. A plurality of stages of sockets are installed on the test board. Each socket is configured to be connected to a device under test (DUT). The sockets of each stage are connected to one of a plurality of different testing devices. Each testing device is configured to perform a unique test on all the DUTs of a corresponding stage.

Abstract: A multichip and method of testing a multichip, the multichip including a control chip having a central processing unit (CPU) and a plurality of memories, each memory of the plurality of memories storing information related to testing the multichip, comprises connecting one of the memories to the control chip; reading, by the CPU, stored memory information from the connected one of the memories to confirm the connected one of the memories; generating a test pattern relating to the connected one of the memories confirmed by the CPU, and testing the connected one of the memories according to the test pattern.

Abstract: A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control signal so as to control a supply of the first or second voltage to the MOS logic; and a fuse unit disposed between the supply terminal of the first voltage or the second voltage and the switching transistor unit, for cutting off a supply of the first or second voltage to the switching transistor unit by a selective cut based on a test result. Whereby, a product development or production difficulty or a yield decrease based on a performance drop or leakage current increase in a circuit having a power gate or MTCMOS may be improved. In addition, a product development delay caused by a mask revision required at a transistor level may be improved in a revision of an NMOS or PMOS transistor.

Abstract: A semiconductor package comprises a plurality of pads disposed along a surface edge of a semiconductor chip, a plurality of mounting bumps formed on a surface of the semiconductor chip and disposed away from the plurality of pads at a predetermined distance, a plurality of redistribution connecting wires for electrically connecting the plurality of pads to the plurality of mounting bumps, and a plurality of test bumps disposed on the plurality of pads.