Patents by Inventor Jin Ku Lee

Jin Ku Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10450482
    Abstract: Provided are: a composition for a window film; a flexible window film formed therefrom; and a flexible display device comprising the same, wherein the composition contains: a siloxane resin comprising chemical Chemical Formula 1 or 2 or a mixture thereof; a cross-linking agent; and an initiator, the cross-linking agent being contained in a content of about 10-30 parts by weight on the basis of 100 parts by weight of the siloxane resin or the mixture thereof.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: October 22, 2019
    Assignees: Samsung SDI Co., Ltd., Samsung Electronics Co., Ltd.
    Inventors: Joo Hui Kim, Si Kyun Park, Kyoung Ku Kang, Sung Han Kim, Jung Hyo Lee, Jin Hee Choi
  • Publication number: 20190295471
    Abstract: A pixel includes an organic light emitting diode (OLED), a pixel circuit, and first and second transistors. The OLD includes a cathode electrode connected to a second power source. The pixel circuit includes a driving transistor having a gate electrode initialized by a third power source. The driving transistor controls the amount of current flowing from a first power source to the second power source via the OLED. The first transistor is connected between a fourth power source and the second power source and an anode electrode of the OLED. The first transistor is turned on based on a scan signal is supplied to a scan line. The second transistor is connected between a data line and the pixel circuit. The second transistor is turned on when the scan signal is supplied to the ith scan line.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: JIN TAE JEONG, Min Ku Lee, Ji Hyun Ka, Tae Hoon Kwon, Seung Kyu Lee, Seung Ji Cha
  • Publication number: 20190287457
    Abstract: A stage includes an output, an input, signal processors, and a stabilizer. The output supplies a voltage of a first or second power source to an output terminal based on voltages of first and second nodes. The input controls voltages of third and fourth nodes based on signals to a first and second input terminals. A first signal processor controls the voltage of the first node based on the voltage of the second node. A second signal processor is connected to a fifth node and controls the voltage of the first node based on a signal to a third input terminal. A third signal processor controls the voltage of the fourth node based on the voltage of the third node and the signal to the third input terminal. The stabilizer is connected between the second signal processor and input to control voltage drop widths of the third and fourth nodes.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Inventors: Seung Kyu LEE, Seung Ji CHA, Ji Hyun KA, Tae Hoon KWON, Min Ku LEE, Jin Tae JEONG
  • Patent number: 10413579
    Abstract: The present invention relates to a composition for preventing or treating asthma comprising a Pistacia weinmannifolia J. Poiss. ex Franch extract or a fraction thereof. The Pistacia weinmannifolia J. Poiss. ex Franch extract or the fraction thereof according to the present invention does not exhibit toxicity, inhibits the generation of NO, IL-4, IL-5, and IL-13 and the generation of reactive oxygen species in the bronchial tubes, and has significantly induced the alleviation of airway hyperresponsiveness, inhibition of the infiltration of inflammatory cells into the bronchial tubes, and reduction of inflammatory cells in bronchoalveolar lavage fluid in an ovalbumin-induced asthma mouse model. In addition, the Pistacia weinmannifolia J. Poiss.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: September 17, 2019
    Assignee: Korea Research Institute of Bioscience and Biotechnology
    Inventors: Kyung Seop Ahn, Sei Ryang Oh, Ok Kyoung Kwon, In Sik Shin, Hyung Won Ryu, Sang Woo Lee, Joong Ku Lee, Hyeong Kyu Lee, Sang Ho Choi, Doo Young Kim, Jung Hee Kim, Li Wan Yi, Jin Hang
  • Publication number: 20190244704
    Abstract: A dietary habit management apparatus and method are provided. The dietary habit management apparatus includes a bio-signal acquirer configured to acquire a bio-signal of a user, and a processor configured to obtain a total peripheral resistance (TPR) reflected index, from the bio-signal that is acquired by the bio-signal acquirer, and determine whether the user has eaten food, based on the TPR reflected index.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 8, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn Ho Kim, Byung Hoon Ko, Yunseo Ku, Yong Joo Kwon, Ui Kun Kwon, Young Soo Kim, Jin Young Park, Jong Wook Lee, Dae Geun Jang, Chang Mok Choi, Jae Min Kang, Seung Woo Noh, Sang Yun Park, Chang Soon Park, Seung Keun Yoon
  • Patent number: 10364289
    Abstract: The present disclosure relates to an antibody binding to Neuropilin 1 (NRP1) or an antigen-binding fragment thereof, a nucleic acid encoding the same, a vector comprising the nucleic acid, a cell transformed with the vector, a method for preparing the antibody or the antigen-binding fragment thereof, an antibody-drug conjugate comprising the antibody or the antigen-binding fragment thereof, and a composition thereof for preventing or treating a cancer.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG LIFE PUBLIC WELFARE FOUNDATION
    Inventors: Do-Hyun Nam, Yeup Yoon, Jae Hyun Lee, Jin Ku Lee
  • Publication number: 20190206978
    Abstract: A display device includes a substrate including a first pixel region, a second pixel region having an area smaller than that of the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a second pixel provided in the second pixel region, a second line connected to the second pixel, an extension line extended to the peripheral region, a dummy part located in the peripheral region to overlap with the extension line, a power line connected to the first and second pixel regions, and a connection line located in the peripheral region to be connected to the dummy part, the connection line being electrically connected to a portion of the second pixel region, wherein the second pixel region includes a first sub-pixel region connected to the connection line and a second sub-pixel region except the first sub-pixel region.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Keon Woo KIM, Ji Hyun KA, Tae Hoon KWON, Ho Kyoon KWON, Min Ku LEE, Zail LHEE, Jin Tae JEONG, Seung Ji CHA, Byung Du AHN, Jeong Ho LEE
  • Patent number: 10319306
    Abstract: A pixel includes an organic light emitting diode (OLED), a pixel circuit, and first and second transistors. The OLD includes a cathode electrode connected to a second power source. The pixel circuit includes a driving transistor having a gate electrode initialized by a third power source. The driving transistor controls the amount of current flowing from a first power source to the second power source via the OLED. The first transistor is connected between a fourth power source and the second power source and an anode electrode of the OLED. The first transistor is turned on based on a scan signal is supplied to a scan line. The second transistor is connected between a data line and the pixel circuit. The second transistor is turned on when the scan signal is supplied to the ith scan line.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Tae Jeong, Min Ku Lee, Ji Hyun Ka, Tae Hoon Kwon, Seung Kyu Lee, Seung Ji Cha
  • Patent number: 10311781
    Abstract: A stage includes an output, an input, signal processors, and a stabilizer. The output supplies a voltage of a first or second power source to an output terminal based on voltages of first and second nodes. The input controls voltages of third and fourth nodes based on signals to a first and second input terminals. A first signal processor controls the voltage of the first node based on the voltage of the second node. A second signal processor is connected to a fifth node and controls the voltage of the first node based on a signal to a third input terminal. A third signal processor controls the voltage of the fourth node based on the voltage of the third node and the signal to the third input terminal. The stabilizer is connected between the second signal processor and input to control voltage drop widths of the third and fourth nodes.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Kyu Lee, Seung Ji Cha, Ji Hyun Ka, Tae Hoon Kwon, Min Ku Lee, Jin Tae Jeong
  • Publication number: 20190154666
    Abstract: The present invention relates to a method for screening drug candidates for treating a disease using the interaction between calcium and phosphatidylinositol phosphate. Particularly in the present invention, it was confirmed that the concentration of calcium was increased in the obesity induced insulin resistance animal model and the increased calcium concentration inhibited the migration of Akt protein containing PH domain and the signal transduction, while the protein containing C2 domain was able to migrate to the cell membrane by binding to calcium/PIP complex even under the condition of high calcium concentration. Therefore, the investigation of the interaction between calcium and PIP can be a useful method for screening of drug candidates for treating metabolic disease, cancer or hypertension.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 23, 2019
    Inventors: Byung-Chul Oh, Jin Ku Kang, Ok Hee Kim, Cheol Soon Lee
  • Publication number: 20190153051
    Abstract: The present invention relates to a fusion protein consisting of a C2 domain and an Akt protein fragment, particularly the fragment consisting of the amino acid residues ranging from the 111th to the 480th amino acids from the N-terminus of the Akt protein, and a use of the said fusion protein. More specifically, the fusion protein of the present invention increases the Akt protein activity even under the condition of high calcium concentration, reduces body weight and fat in an animal model treated with a high fat diet infected with adenovirus containing the fusion protein above, improves insulin resistance and improves fatty liver, so that the fusion protein comprising the C2 domain and the fragment consisting of the amino acid residues ranging from the 111th to 480th amino acids from the N-terminus of Akt protein can be effectively used for the treatment of metabolic disease.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 23, 2019
    Inventors: Byung-Chul Oh, Jin Ku Kang, Ok Hee Kim, Cheol Soon Lee
  • Publication number: 20170291948
    Abstract: The present disclosure relates to an antibody binding to Neuropilin 1 (NRP1) or an antigen-binding fragment thereof, a nucleic acid encoding the same, a vector comprising the nucleic acid, a cell transformed with the vector, a method for preparing the antibody or the antigen-binding fragment thereof, an antibody-drug conjugate comprising the antibody or the antigen-binding fragment thereof, and a composition thereof for preventing or treating a cancer.
    Type: Application
    Filed: December 3, 2015
    Publication date: October 12, 2017
    Inventors: Do-Hyun Nam, Yeup Yoon, Jae Hyun Lee, Jin Ku Lee
  • Patent number: 9728638
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Publication number: 20160372595
    Abstract: A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: Jong Chul LEE, Min Yong LEE, Jin Ku LEE
  • Publication number: 20160111535
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Jin-Ku LEE, Young-Ho LEE, Mi-Ri LEE
  • Patent number: 9263575
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9076864
    Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: July 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Young-Ho Lee, Mi-Ri Lee
  • Patent number: 9054128
    Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Ku Lee, Jae-Geun Oh, Young-Ho Lee, Mi-Ri Lee, Seung-Beom Baek
  • Patent number: 8901528
    Abstract: A PCRAM device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, and a PN diode formed on the semiconductor substrate and including a layer interposed therein to suppress thermal diffusion of ions.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Ku Lee, Min Yong Lee, Jong Chul Lee
  • Publication number: 20140299918
    Abstract: A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region.
    Type: Application
    Filed: July 25, 2013
    Publication date: October 9, 2014
    Applicant: SK hynix Inc.
    Inventors: Jong Chul LEE, Min Yong LEE, Jin Ku LEE