Patents by Inventor Jin-Kyoung Jung

Jin-Kyoung Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8253478
    Abstract: An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Kyoung Jung, Jung-Bae Lee, Kyu-Hyoun Kim
  • Publication number: 20090085650
    Abstract: An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.
    Type: Application
    Filed: December 1, 2008
    Publication date: April 2, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Kyoung Jung, Jung-Bae Lee, Kyu-Hyoun Kim
  • Patent number: 7269078
    Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: September 11, 2007
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Sung-min Seo, Chul-soo Kim, Kyu-hyoun Kim, Jin-kyoung Jung
  • Patent number: 7123520
    Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: October 17, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-min Seo, Chul-soo Kim, Kyu-hyoun Kim, Jin-kyoung Jung
  • Publication number: 20060215462
    Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 28, 2006
    Inventors: Sung-min Seo, Chul-soo Kim, Kyu-hyoun Kim, Jin-kyoung Jung
  • Patent number: 6999375
    Abstract: A synchronous semiconductor device and a method for preventing coupling between data buses. The synchronous semiconductor device supports at least two kinds of bit configuration modes and includes a first data bus and a second data bus. The first data bus is used to transmit data in a first bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode. The second data bus is used to transmit data in the first bit configuration mode and a second bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode and the second bit configuration mode. The first data bus and the second data bus are arranged alternately. In using the device and method, it is possible to prevent coupling between the data buses without additional shielding lines by using the same kind of data bus, which is not used to transmit data, as the shielding line.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: February 14, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jin-kyoung Jung, Kyu-hyoun Kim
  • Publication number: 20050111273
    Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.
    Type: Application
    Filed: July 2, 2004
    Publication date: May 26, 2005
    Inventors: Sung-min Seo, Chul-soo Kim, Kyu-hyoun Kim, Jin-kyoung Jung
  • Publication number: 20040212422
    Abstract: An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.
    Type: Application
    Filed: March 12, 2004
    Publication date: October 28, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Kyoung Jung, Jung-Bae Lee, Kyu-Hyoun Kim
  • Publication number: 20040063271
    Abstract: Provided are a synchronous semiconductor device and a method for preventing coupling between data buses. The synchronous semiconductor device supports at least two kinds of bit configuration modes and includes a first data bus and a second data bus. The first data bus is used to transmit data in a first bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode. The second data bus is used to transmit data in the first bit configuration mode and a second bit configuration mode and used as a shielding line in a configuration mode other than the first bit configuration mode and the second bit configuration mode. The first data bus and the second data bus are arranged alternately. In using the device and method, it is possible to prevent coupling between the data buses without additional shielding lines by using the same kind of data bus, which is not used to transmit data, as the shielding line.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 1, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Kyoung Jung, Kyu-Hyoun Kim
  • Patent number: 6229756
    Abstract: A semiconductor memory device is provided that is capable of operating normally and having its operating speed unaffected, even when column address lines for transmitting column addresses are greatly loaded and even when the loads on the column address lines are simultaneously different from one another. The semiconductor memory device includes a column selection line driver for receiving decoded addresses and driving column selection lines of a memory cell array in response to a column selection line control signal, a column selection line control signal generator for receiving buffered column address data, and for generating the column selection line control signal in response to an internal clock signal and one of a first control signal and a second control signal, and a control signal generator for generating the first and second control signals in response to the internal clock signal, an externally-input column address strobe signal, and an externally-input write enable signal.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: May 8, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Kyoung Jung, Chi-wook Kim