Patents by Inventor Jin Kyoung PARK
Jin Kyoung PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11658149Abstract: A semiconductor package including: a base layer; and a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks.Type: GrantFiled: March 12, 2021Date of Patent: May 23, 2023Assignee: SK hynix Inc.Inventor: Jin Kyoung Park
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Patent number: 11462511Abstract: A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.Type: GrantFiled: October 14, 2020Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: Ju Il Eom, Jin Kyoung Park
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Publication number: 20220189914Abstract: A semiconductor package including: a base layer; and a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks.Type: ApplicationFiled: March 12, 2021Publication date: June 16, 2022Applicant: SK hynix Inc.Inventor: Jin Kyoung PARK
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Publication number: 20220189924Abstract: A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.Type: ApplicationFiled: March 12, 2021Publication date: June 16, 2022Applicant: SK hynix Inc.Inventor: Jin Kyoung PARK
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Patent number: 11270958Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.Type: GrantFiled: August 12, 2020Date of Patent: March 8, 2022Assignee: SK hynix Inc.Inventors: Ju Il Eom, Jin Kyoung Park, Han Jun Bae
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Publication number: 20220013499Abstract: A semiconductor package includes a sub semiconductor package disposed over a substrate. The sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer. The redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion and a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer. The semiconductor package also includes a sub signal interconnector, sub power interconnector, and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.Type: ApplicationFiled: October 14, 2020Publication date: January 13, 2022Applicant: SK hynix Inc.Inventors: Ju Il EOM, Jin Kyoung PARK
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Publication number: 20210366847Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.Type: ApplicationFiled: August 12, 2020Publication date: November 25, 2021Applicant: SK hynix Inc.Inventors: Ju Il EOM, Jin Kyoung PARK, Han Jun BAE
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Patent number: 10497671Abstract: A semiconductor package may include a first chip stack, a second chip stack, and a third chip stack. The third chip stack may include third semiconductor chips, the third chip stack coupled to both of the first and second chip stacks.Type: GrantFiled: August 8, 2018Date of Patent: December 3, 2019Assignee: SK hynix Inc.Inventors: Kyung Hwan Cho, Ga Hyun No, Jin Kyoung Park, Yong Kuk Kim
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Publication number: 20190221542Abstract: A semiconductor package may include a first chip stack, a second chip stack, and a third chip stack. The third chip stack may include third semiconductor chips, the third chip stack coupled to both of the first and second chip stacks.Type: ApplicationFiled: August 8, 2018Publication date: July 18, 2019Applicant: SK hynix Inc.Inventors: Kyung Hwan CHO, Ga Hyun NO, Jin Kyoung PARK, Yong Kuk KIM
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Patent number: 10262972Abstract: A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.Type: GrantFiled: December 1, 2017Date of Patent: April 16, 2019Assignee: SK hynix Inc.Inventors: Seung Yeop Lee, Jin Kyoung Park
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Patent number: 10217722Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.Type: GrantFiled: May 3, 2018Date of Patent: February 26, 2019Assignee: SK hynix Inc.Inventor: Jin Kyoung Park
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Publication number: 20180342481Abstract: A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.Type: ApplicationFiled: December 1, 2017Publication date: November 29, 2018Applicant: SK hynix Inc.Inventors: Seung Yeop LEE, Jin Kyoung PARK
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Publication number: 20180254261Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.Type: ApplicationFiled: May 3, 2018Publication date: September 6, 2018Applicant: SK hynix Inc.Inventor: Jin Kyoung PARK
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Patent number: 9991226Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.Type: GrantFiled: April 19, 2017Date of Patent: June 5, 2018Assignee: SK hynix Inc.Inventor: Jin Kyoung Park
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Publication number: 20180122771Abstract: A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.Type: ApplicationFiled: April 19, 2017Publication date: May 3, 2018Applicant: SK hynix Inc.Inventor: Jin Kyoung PARK